Embodiments of a reference path circuit and communication device are generally described herein. The reference path circuit may include an injection locked multiplier (ILM) and a group of one or more buffer amplifiers. The ILM may receive a sinusoidal reference signal from a reference oscillator at a reference frequency. The ILM may generate a sinusoidal ILM output signal at an ILM output frequency that is based on an integer multiple of the reference frequency. The integer multiple of the reference frequency may be within a locking range of the ILM that may be based on a resonant frequency of the ILM. The group of one or more buffer amplifiers may generate an output clock signal for input to the frequency synthesizer. The output clock signal may be based on a sign function of the ILM output signal.

A subsampling motion detector configured to detect motion information of an object under measurement receives a first wireless radio frequency (RF) signal and transmits a second wireless RF signal, the first wireless RF signal being generated by reflecting the second wireless RF signal from the object. The subsampling motion detector includes a controllable oscillator outputting an oscillation signal, wherein the first wireless RF signal is injected to the controllable oscillator for controlling the controllable oscillator through injecting locking. The subsampling motion detector further including a subsampling phase detector (SSPD) generating a control signal according to the oscillation signal generated by the controllable oscillator and a reference frequency, the SSPD outputting the control signal to the controllable oscillator for controlling the controllable oscillator, the oscillation signal of the controllable oscillator being locked to a multiple of the reference frequency and the control signal representing the motion information of the object.

Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.

A circuit includes a first digital controlled oscillator and a second digital controlled oscillator coupled to the first digital controlled oscillator. A skew detector is connected to determine a skew between outputs of the first digital controlled oscillator and the second digital controlled oscillator, and a decoder is utilized to output a control signal, based on the skew, to modify a frequency of the first digital controlled oscillator using a switched capacitor array to reduce or eliminate the skew. A differential pulse injection oscillator circuit and a pulse injection signal generator circuit are also provided,

A signal distribution system includes: a first signal divider arranged to generate a first output oscillating signal according to a first input oscillating signal; a second signal divider arranged to generate a second output oscillating signal according to the first input oscillating signal; a first transmitting channel coupled to the first signal divider and the second divider for transmitting the first input oscillating signal to the first signal divider and the second signal divider; and a second transmitting channel coupled to the first signal divider and the second divider for transmitting a second input oscillating signal to the first signal divider and the second signal divider; wherein the first input oscillating signal has a first frequency, the second input oscillating signal has a second frequency, and the second frequency is smaller than the first frequency.

A signal distribution system includes: a first signal divider arranged to generate a first output oscillating signal according to a first input oscillating signal; a second signal divider arranged to generate a second output oscillating signal according to the first input oscillating signal; a first transmitting channel coupled to the first signal divider and the second divider for transmitting the first input oscillating signal to the first signal divider and the second signal divider; and a second transmitting channel coupled to the first signal divider and the second divider for transmitting a second input oscillating signal to the first signal divider and the second signal divider; wherein the first input oscillating signal has a first frequency, the second input oscillating signal has a second frequency, and the second frequency is smaller than the first frequency.

An object detection system for autonomous vehicle, comprising a radar unit and at least one ultra-low phase noise frequency synthesizer, is provided. The radar unit configured for detecting the presence and characteristics of one or more objects in various directions. The radar unit may include a transmitter for transmitting at least one radio signal; and a receiver for receiving the at least one radio signal returned from the one or more objects. The ultra-low phase noise frequency synthesizer may utilize Clocking device, Sampling Reference PLL, at least one fixed frequency divider, DDS and main PLL to reduce phase noise from the returned radio signal. This proposed system overcomes deficiencies of current generation state of the art Radar Systems by providing much lower level of phase noise which would result in improved performance of the radar system in terms of target detection, characterization etc. Further, a method or autonomous vehicle is also disclosed.

An object detection system for autonomous vehicle, comprising a radar unit and at least one ultra-low phase noise frequency synthesizer, is provided. The radar unit configured for detecting the presence and characteristics of one or more objects in various directions. The radar unit may include a transmitter for transmitting at least one radio signal; and a receiver for receiving the at least one radio signal returned from the one or more objects. The ultra-low phase noise frequency synthesizer may utilize Clocking device, Sampling Reference PLL, at least one fixed frequency divider, DDS and main PLL to reduce phase noise from the returned radio signal. This proposed system overcomes deficiencies of current generation state of the art Radar Systems by providing much lower level of phase noise which would result in improved performance of the radar system in terms of target detection, characterization etc. Further, a method or autonomous vehicle is also disclosed.

The present disclosure provides a clock data recovery apparatus. The clock data recovery apparatus includes a phase detection circuit, a digital filter, a phase-interpolating circuit and an oscillator circuit. The phase detection circuit receives and samples a data signal according to multiple reference clock signals having different phases, to generate a phase detection result. The digital filter performs accumulation on the phase detection result, to generate a phase-adjusting signal. The phase interpolator circuit performs phase adjustment on a source clock signal according to the phase-adjusting signal, in order to generate an injection clock signal. The oscillator circuit generates the reference clock signals according to the injection clock signal, in which the phases of the reference clock signals follow the phase of the injection clock signal.

An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.