A signal distribution system includes: a first signal divider arranged to generate a first output oscillating signal according to a first input oscillating signal; a second signal divider arranged to generate a second output oscillating signal according to the first input oscillating signal; a first transmitting channel coupled to the first signal divider and the second divider for transmitting the first input oscillating signal to the first signal divider and the second signal divider; and a second transmitting channel coupled to the first signal divider and the second divider for transmitting a second input oscillating signal to the first signal divider and the second signal divider; wherein the first input oscillating signal has a first frequency, the second input oscillating signal has a second frequency, and the second frequency is smaller than the first frequency.

A frequency synthesis device, including: a first generator configured to generate a periodical signal with a frequency f.sub.1; a second generator, coupled to the first generator and generating from the signal with a frequency f.sub.1 a signal S.sub.G corresponding to a train of oscillations with a frequency substantially equal to N.Math.f.sub.1, with a duration lower than T.sub.1=1/f.sub.1 and periodically repeated at the frequency f.sub.1; a third generator generating, from the signal S.sub.G, m periodical signals S.sub.LO.sub._.sub.CH1 to S.sub.LO.sub._.sub.CHm with frequency spectra each include a main line with a frequency f.sub.LO.sub._.sub.CHi corresponding to an integer multiple of f.sub.1, with 1≦i≦m, the third generator operating as a band-pass filter applied to the signal S.sub.G and discarding from the frequency spectra of each of the periodical signals S.sub.LO.sub._.sub.CH1 to S.sub.LO.sub._.sub.CHm lines other than the main line with a frequency f.sub.LO.sub._.sub.CHi.

A frequency synthesis device, including: a first generator configured to generate a periodical signal with a frequency f.sub.1; a second generator, coupled to the first generator and generating from the signal with a frequency f.sub.1 a signal S.sub.G corresponding to a train of oscillations with a frequency substantially equal to N.Math.f.sub.1, with a duration lower than T.sub.1=1/f.sub.1 and periodically repeated at the frequency f.sub.1; a third generator generating, from the signal S.sub.G, m periodical signals S.sub.LO.sub._.sub.CH1 to S.sub.LO.sub._.sub.CHm with frequency spectra each include a main line with a frequency f.sub.LO.sub._.sub.CHi corresponding to an integer multiple of f.sub.1, with 1≦i≦m, the third generator operating as a band-pass filter applied to the signal S.sub.G and discarding from the frequency spectra of each of the periodical signals S.sub.LO.sub._.sub.CH1 to S.sub.LO.sub._.sub.CHm lines other than the main line with a frequency f.sub.LO.sub._.sub.CHi.

A frequency adjusting apparatus used in a processing chip operated at an operation frequency according to a power is provided that includes a clock supplying circuit, a frequency division circuit and a control circuit. The clock supplying circuit outputs one of clock signals as a supplied clock signal. The frequency division circuit performs frequency division on the supplied clock signal according to a parameter to generate an output clock signal. The control circuit determines a combination of a selected clock signal and a value of the parameter for gradually increasing the frequency of the output clock signal during the increasing of the voltage value that passes through voltage value sections, wherein when the voltage value is determined to be larger than a second threshold value and when the voltage value sections correspond to higher voltage values, the selected clock signal has a higher frequency.

A frequency adjusting apparatus used in a processing chip operated at an operation frequency according to a power is provided that includes a clock supplying circuit, a frequency division circuit and a control circuit. The clock supplying circuit outputs one of clock signals as a supplied clock signal. The frequency division circuit performs frequency division on the supplied clock signal according to a parameter to generate an output clock signal. The control circuit determines a combination of a selected clock signal and a value of the parameter for gradually increasing the frequency of the output clock signal during the increasing of the voltage value that passes through voltage value sections, wherein when the voltage value is determined to be larger than a second threshold value and when the voltage value sections correspond to higher voltage values, the selected clock signal has a higher frequency.

A frequency doubler (tripler, or quadrupler) employs current re-use coupled oscillator technique to enhance phase noise without increasing current consumption. Frequency doubler uses coupling between two oscillators running at different frequencies; a first oscillator is running at the target frequency and a second oscillator is running at half the frequency. The coupling between the two oscillators is via a transformer having a primary transformer coil and a secondary transformer coil. The first oscillator comprises a differential inductor, coarse/fine tuning capacitor arrays, and an n-type trans-conductor (GM). A virtual ground node of the n-type GM is coupled to one side of the primary transformer coil and the other side of the primary coil is coupled to the center tap of the secondary coil. The second oscillator comprises the secondary coil, coarse/fine tuning capacitor arrays, n-type GM, frequency tracking loop (FTL) and 2.sup.nd-harmonic LC filter network.

Apparatus and methods for controlling a clock signal are provided. In certain embodiments, a semiconductor die includes a core circuit and a clock interface circuit that provides a clock signal to the core circuit. The clock interface circuit includes an oscillator for generating an oscillator signal, and a comparator for controlling operation of the clock interface circuit in a selected clock control mode based on comparing an electrical characteristic of the clock interface pin to a comparison threshold. The selected clock control mode is chosen from a first clock control mode in which the clock interface circuit generates the clock signal based on an input clock signal received on a clock interface pin, or a second clock control mode in which the clock interface circuit generates the clock signal based on the oscillator signal.

Apparatus and methods for controlling a clock signal are provided. In certain embodiments, a semiconductor die includes a core circuit and a clock interface circuit that provides a clock signal to the core circuit. The clock interface circuit includes an oscillator for generating an oscillator signal, and a comparator for controlling operation of the clock interface circuit in a selected clock control mode based on comparing an electrical characteristic of the clock interface pin to a comparison threshold. The selected clock control mode is chosen from a first clock control mode in which the clock interface circuit generates the clock signal based on an input clock signal received on a clock interface pin, or a second clock control mode in which the clock interface circuit generates the clock signal based on the oscillator signal.

Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.

Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.