A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.

Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.

The present disclosure discloses a digital loop filter in an all-digital phase-locked loop. The digital loop filter may include a selection circuit configured to output one of a first data signal and a second data signal as valid data, a first operation circuit configured to output a first operation signal by adding or subtracting the valid data and a first register signal, a first register circuit configured to register the first operation signal and output the first operation signal as the first register signal, a second operation circuit configured to output a second operation signal by adding or subtracting a value of at least one bit of the valid data and the first register signal, and a second register circuit configured to store the second operation signal and output the second operation signal as a control signal.

An all-digital phase-locked loop (ADPLL) circuit and a calibration method thereof are provided. The ADPLL circuit includes a digitally controlled oscillator (DCO) circuit, a phase detector circuit, and a calibration circuit coupled between the DCO circuit and the phase detector circuit. The DCO circuit generates a clock signal according to a frequency control signal. The phase detector circuit generates a phase error value according to a reference signal and the clock signal. More particularly, after the ADPLL circuit performs a locking operation for a period of time, the frequency control signal is tied at a locked value which is obtained when the ADPLL circuit performs the locking operation, and the calibration circuit may modify a current of at least one current source within the DCO circuit according to the phase error value.

The present disclosure discloses an all-digital phase-locked loop. The all-digital phase-locked loop may include a time-to-digital conversion circuit configured to convert phase differences between a reference signal and a feedback signal into respective digital values and to output a first data signal and a second data signal corresponding to the respective digital values, a digital loop filter configured to select one of the first data signal and the second data signal as valid data and output a control signal by operating the valid data and a first register signal, a digitally controlled oscillator configured to generate an oscillation signal and control a frequency of the oscillation signal in response to the control signal, and a divider configured to divide the oscillation signal and output the feedback signal to the time-to-digital conversion circuit.

An all-digital-phase-locked-loop (ADPLL) includes a digitally controlled oscillator (DCO) arranged to generate a DCO output signal, and a feedback loop comprising a set of components for controlling the DCO. The set of components comprise: a time-to-digital converter (TDC) arranged to generate a TDC output code indicative of the phase difference between the reference signal and the enable signal measured within the predetermined observation window; a subset of components arranged to generate the enable signal from the DCO output signal; and an offset calibration system connected to the TDC output, which when activated is arranged to evaluate the difference between the first and second offset delay values by monitoring the TDC output code generated over a predetermined period of time, and to adjust the difference to position the predetermined observation window with respect to the reference signal.

Power consumption of a time-to-digital converter (TDC) used in a phase locked loop (ADPLL) is suppressed. The time-to-digital converter includes an analog-to-digital converter and a current source circuit. The analog-to-digital converter includes a predetermined charge capacitor. The current source circuit supplies a charge current that charges the charge capacitor of the analog-to-digital converter with a charge. The charge current supplied by the current source circuit is supplied so that a charge voltage at the time of charging the charge capacitor of the analog-to-digital converter with the charge current has a constant gradient with respect to a charge time.

A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.

According to one embodiment, a semiconductor integrated circuit device includes an oscillator, a frequency divider, and a control circuit. The oscillator is configured to oscillate at a variable oscillation frequency. The frequency divider is configured to oscillate at a variable free-running oscillation frequency, and has a frequency dividing range that transitions according to a variation in the free-running oscillation frequency. The control circuit is configured to control the oscillator to vary the oscillation frequency during a calibration operation that adjusts the oscillation frequency and is configured to control the frequency divider to cause the frequency dividing range to transition based on an amount of variation of the oscillation frequency.