With respect to a phase locked loop (PLL) circuit that receives a first reference clock and generates an output clock, the PLL circuit includes a delay circuit that delays the first reference clock to generate a second reference clock, a feedback circuit that generates a control signal based on a phase difference between the second reference clock and a feedback clock, an oscillator that oscillates at a frequency determined based on the control signal to generate the output clock, and a divider that divides the output clock in the on state. The PLL circuit switches between a first mode and a second mode, the feedback clock in the first mode is a signal obtained by retiming an output of the divider with the output clock, and the feedback clock in the second mode is a signal obtained by retiming the first reference clock with the output clock.

A delay measurement circuit includes a first skew circuit disposed proximate to a first bonding pad configured to receive a first clock signal having a first frequency. The delay measurement circuit includes a second skew circuit disposed proximate to a second bonding pad configured to receive a second clock signal having a second frequency. The first and second skew circuits each have a first mode of operation as zero-delay-return path and a second mode of operation as a synchronized pass path. The delay measurement circuit includes a pair of conductive traces coupled to the first skew circuit, another pair of conductive traces coupled to the second skew circuit, a time-to-digital converter circuit, and a switch circuit configured to selectively couple the time-to-digital converter circuit to the first skew circuit via the pair of conductive traces and the second skew circuit via the other pair of conductive traces.

We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ⅔ the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ⅔ the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ⅓ the first frequency or about ⅓ the second frequency during the duty cycle.

A wireless communication device for asymmetrical frequency spreading including a processor configured to receive a frequency band message comprising a maximum difference and a minimum difference, wherein the maximum difference is between a maximum frequency of a sub-band and a signal frequency, and wherein the minimum difference is between the minimum frequency of the sub-band and the signal frequency compare the maximum difference and the minimum difference with each other; and generate a frequency shift based on the comparison.

A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

A phase correcting device includes a local oscillator that includes an all digital phase-locked loop configured to output a local oscillation signal, a first phase detector configured to detect a phase of the local oscillation signal to output the phase of the local oscillation signal, a reference phase device configured to generate a quasi-reference phase corresponding to a reference phase of the local oscillation signal to output the quasi-reference phase, based on a reference clock, a second phase detector configured to detect a fluctuation amount of a phase of the local oscillator, based on the phase detected by the first phase detector and the quasi-reference phase, and a correction circuit configured to correct the phase of the inputted signal by using a detection result of the second phase detector.

In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.

A circuit for facilitating random edge injection locking of an oscillator comprises a clock signal and a digitally controlled delay line, where the digitally controlled delay line is configured to delay the clock signal, thereby generating a delayed clock signal. The circuit further comprises an edge selector configured to generate a phase select signal with a random pulse sequence. Moreover, the circuit comprises a pulse generator downstream to the digitally controlled delay line configured to generate injection pulses from the delayed clock signal for at least two phases of the oscillator based on the phase select signal.

A delay measurement circuit includes a first skew circuit disposed proximate to a first bonding pad configured to receive a first clock signal having a first frequency. The delay measurement circuit includes a second skew circuit disposed proximate to a second bonding pad configured to receive a second clock signal having a second frequency. The first and second skew circuits each have a first mode of operation as zero-delay-return path and a second mode of operation as a synchronized pass path. The delay measurement circuit includes a pair of conductive traces coupled to the first skew circuit, another pair of conductive traces coupled to the second skew circuit, a time-to-digital converter circuit, and a switch circuit configured to selectively couple the time-to-digital converter circuit to the first skew circuit via the pair of conductive traces and the second skew circuit via the other pair of conductive traces.