A phase correction apparatus includes an inductor joined to a series capacitor to produce phase-corrected output having a load voltage and a load current. A phase detector is joined to the series capacitor and has a phase angle output proportional to a phase angle between the voltage and current. Logic circuitry or a processor is joined to receive the phase angle output and provide switch control value outputs to switches connected to the logic circuitry. A bank of parallel capacitors are joined to the switches. The switch control value outputs activate joined parallel capacitors to adjust reactance provided to the phase-corrected output to produce an adjusted output. In a further embodiment parallel capacitors are iterated to produce the adjusted output.

A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.

A circuit includes a first amplifier that first compares a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operation period, second compares the ramp signal and an image signal of the pixel signal in a second operation period, and generates a first output signal in the first and second operation periods based on first and second comparison results; and a second amplifier that charges a capacitor in response to a second auto-zero signal in a second auto-zero period, stops an operation of the second amplifier from a time point at which the second auto-zero period ends to a time point at which the first operation period starts, and generates a second output signal based on the first output signal in the first operation period and the second operation period.

A method, which is applied in a driving circuit including an analog-to-digital convertor (ADC) and a switching circuit including an inductor and coupled to a load, includes steps of: performing an analog-to-digital conversion on a load voltage of the load at a first rate; and producing at least a current pulse flowing through the inductor at a second rate. Wherein, each current pulse among the at least a current pulse is accomplished within a second cycle corresponding to the second rate, all of the at least a current pulse are accomplished within a first cycle corresponding to the first rate, and a first length of the first cycle is longer than twice of a second length of the second cycle.

A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.

A data channel includes a power constrained first channel portion to receive energy from a limited power source and a non-power constrained second channel portion to receive energy from a different power source than the first channel portion. The first channel portion includes an ADC circuit to output an ADC data sample, a first transmitter circuit configured to serially transmit data that includes ON bits and OFF bits, and logic circuitry configured to derive transmit data from the ADC data sample. The transmitter circuit uses more energy transmitting the ON bits than the OFF bits, and the derived transmit data has a reduced number of the ON bits from the ADC data sample. The second channel portion includes a first receiver circuit to receive the derived transmit data from the first transmitter circuit of the first channel portion.

An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.

A chip state monitoring circuit based on a self-balancing differential signal integration and amplification circuit is provided. The chip state monitoring circuit is built in a chip, and can sense a state signal of the chip and transmit the state signal to a chip configuration circuit after performing amplification and analog-to-digital conversion, such that the chip configuration circuit can monitor a state and provide a timely feedback or response, thereby improving reliability and a service life of the chip. The chip state monitoring circuit uses a brand new self-balancing differential signal integration and amplification circuit. With a built-in positive coefficient integration network and negative coefficient balancing network, the self-balancing differential signal integration and amplification circuit can perform amplification by required times to enter a self-balancing stable state, thereby achieving fixed-multiple amplification without timed reading. The control method is simple and flexible.

An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.

An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.