A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.

An ADC includes a plurality of sub ADCs configured to operate in a time-interleaved manner and a sampling circuit configured to receive an analog input signal of the ADC, wherein the sampling circuit is common to all sub ADCs. The ADC includes a test signal generation circuit configured to generate a test signal for calibration of the ADC. The sampling circuit has a first input configured to receive the analog input signal and a second input configured to receive the test signal. The sampling circuit includes an amplifier circuit and a first feedback switch connected between an output of the amplifier circuit and an input of the amplifier circuit. The first feedback switch is configured to be closed during a first clock phase and open during a second clock phase, which is non-overlapping with the first clock phase.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current sources, a plurality of calibration DACs, each coupled to a respective one of the plurality of current sources, a reference current source, and a current mirror having a first branch selectively coupled to the plurality of current sources, wherein a second branch of the current mirror is coupled to the reference current source. The DAC system also includes a first error DAC selectively coupled to the first branch and the second branch of the current mirror, and a second error DAC selectively coupled to the first branch and the second branch of the current mirror.

A successive-approximation analog-to-digital converter includes a sampling circuit for sampling an analog input signal to acquire a sampled voltage, and a regenerative comparator for comparing the sampled voltage with a succession of reference voltages to generate, for each reference voltage, a decision bit indicating the comparison result. The converter also includes a digital-to-analog converter which is adapted to generate the succession of reference voltages, in dependence on successive comparison results in the comparator, to progressively approximate the sampled voltage. The regenerative comparator comprises an integration circuit for generating output signals defining the decision bits, and a plurality of regeneration circuits for receiving these output signals. The regeneration circuits are operable, in response to respective control signals, to store respective decision bits defined by successive output signals from the integration circuit.

The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.

The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.

An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.

An electronic device includes a precision reference circuit, which contains a bandgap reference circuit and an offset-correction circuit. The bandgap reference circuit has an output that is coupled to provide a bandgap reference voltage and an intermediate node that is separated from the output by a transimpedance resistor. The offset-correction circuit is coupled to the bandgap reference circuit and includes a DAC. The DAC is coupled to the intermediate node and is also coupled to receive an external digital value. The external digital value determines a fraction of a correction current that will be passed by the DAC.

An AD converter with self-calibration function that does not require an instrument for calibration, and includes: a reference voltage unit that generates a reference voltage; a summation and conversion unit that has two or more unit voltages serving as units of amount of change in a summed voltage, and during conversion, sums up any one unit voltage of the two or more unit voltages until the summed voltage exceeds the reference voltage, with an input voltage being an initial value of the summed voltage; and a control unit including a calibration control section that calibrates the two or more unit voltages and an offset voltage of a comparator at a time of calibration, and a conversion control section that determines a polarity of the offset voltage of the comparator and thereafter converts the input voltage to a digital value during conversion.

The present disclosure provides a circuitry. The circuitry includes a comparator and a signal correlated circuit. The comparator includes a first input terminal, a second input terminal, and an output terminal, The signal correlated circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to receive a first input signal. The second input terminal is coupled to receive a second input signal independent from the first input signal. The first output terminal is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator. The second output terminal is configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The first output signal and the second output signal are correlated.