The present disclosure provides a circuitry. The circuitry includes a comparator and a signal correlated circuit. The comparator includes a first input terminal, a second input terminal, and an output terminal. The signal correlated circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to receive a first input signal. The second input terminal is coupled to receive a second input signal independent from the first input signal. The first output terminal is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator. The second output terminal is configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The first output signal and the second output signal are correlated.

A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.

A calibratable switched-capacitor voltage reference and an associated calibration method are described. The voltage reference includes dynamic diode elements providing diode voltages, input capacitor(s) for sampling input voltages, base-emitter capacitor(s) for sampling one diode voltage with respect to a ground, dynamically trimmable capacitor(s) for sampling the one diode voltage with respect to another diode voltage, and an operational amplifier coupled to the capacitors for providing reference voltage(s) based on the sampled input and diode voltages and on trims of the trimmable capacitor(s). The voltage reference can be configured as a first integrator of a modulator stage of a delta-sigma analog-to-digital converter.

A ramp signal calibration device includes a ramp generator circuit, a detector circuitry, and a calibration circuit. The ramp generator circuit is configured to output a ramp signal according to a set signal and a calibration signal. The detector circuitry is configured to detect the ramp signal or at least one pulse signal associated with the ramp signal, in order to generate at least one control signal. The calibration circuit is configured to generate a calibration signal in response to the at least one control signal, in order to adjust at least one of a falling slope or a rising slope of the ramp signal, or to adjust a duty cycle of the at least one pulse signal.

A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.

An image sensor includes ADCs, each including a comparator receiving a ramp signal and an image signal, and generating a comparator output. Each ADC also includes a counter ceasing to change a digital count value in response to a change in the comparator output. The digital count value has a first resolution. Each ADC also includes a delay line circuit including a delay line generating a first digital value encoding a duration of a period of the counter clock and generating a second digital value encoding a first portion of the period of the counter clock. Each ADC also includes a delay to digital circuit generating a digital output value based on the first and digital values. The digital output value encodes a second value of the ramp signal, where the digital count value has a second resolution that is greater than the first resolution.

In some embodiments, a digital-to-analog converter (DAC) architecture can include an array having a total number of bit cells, and a control system configured to activate a selected number of the total number of bit cells and to deactivate the remaining bit cells. The selected number can be variable, such that the array consumes a quiescent current that depends on the selected number. The control system can be further configured to change the selected number when a signal condition exceeds a threshold duration.

Methods are provided for supervising a motor control unit with at least two separate channels, each of the two channels including at least: means for executing a given application task AS, the application task AS including a plurality of successively executed computations between which latency periods elapse; a first component capable of performing the computations; a second component capable of storing data; the application tasks AS of the channels being capable of communicating. The method comprising includes the following steps: a) detecting a latency period; b) performing, during this latency period, an operating state test of at least one of the components; and c) determining a state of the component corresponding to a failure state or a healthy state.

An error calibration apparatus and method are provided. The method is adapted for calibrating a machine learning (ML) accelerator. The ML accelerator achieves computation by using an analog circuit. An error between an output value of one or more computing layers of a neural network and a corresponding corrected value is determined. The computation of the computing layers is achieved by the analog circuit. A calibration node is generated according to the error. The calibration node is located at the next layer of the computing layers. The calibration node is used to minimize the error. The calibration node is achieved by a digital circuit. Accordingly, error and distortion of the analog circuit could be reduced.

A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.