In some embodiments, a calibration circuit can include a first circuit configured to generate a first output voltage based on a first reference voltage, and a second circuit configured to compare the first output voltage and a second reference voltage. The calibration circuit can further include a calibration block configured to provide an adjustment to the first circuit based on the comparison of the first output voltage and the second reference voltage, with the adjustment being configured to compensate for a change in the first reference voltage. In some embodiments, such a calibration circuit can be utilized for and/or be a part of a digital-to-analog converter for wireless audio applications.

Alignment circuitry including a first clocked latch for receiving a synchronization signal having an enable edge and a target clock signal and outputting an enable signal having an enable edge corresponding to the enable edge of the synchronization signal and synchronized with the target clock signal; a second clocked latch for receiving the enable signal and a delayed target clock signal, being a version of the target clock signal having been delayed by a delay circuit of the clock-controlled circuitry, and outputting a re-timed enable signal having an enable edge corresponding to the enable edge of the enable signal and synchronized with the delayed target clock signal; and gating circuitry for receiving the delayed target clock signal and the re-timed enable signal and to start output of the delayed target clock signal at a timing defined by the enable edge of the re-timed enable signal for controlling the clock-controlled circuitry.

The present invention discloses a DAC method having signal calibration mechanism used in a DAC circuit having thermometer-controlled current sources generating an output analog signal according to a total current thereof and a control circuit. Current offset values of the current sources are retrieved. The current offset values are sorted to generate a turn-on order, in which the current offset values are separated into current offset groups according to the turn-on order, the signs of each neighboring two groups being opposite such that the current offset values cancel each other when the current sources turn on according to the turn-on order to keep an absolute value of a total offset not larger than a half of a largest absolute value of the current offset values. The current sources are turned on based on the turn-on order according to a thermal code included in an input digital signal.

An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.

A ramp voltage generator includes: a ramping cell array including a plurality of ramping current cells; a calibration cell array including a plurality of calibration current cells; and a current-voltage converter suitable for converting a current supplied from activated ramping current cells among the ramping current cells and activated calibration current cells among the calibration current cells into a voltage to generate a ramp voltage.

A system may include ADC circuitry. To test the performance of the ADC circuitry, the system may include ADC testing circuitry coupled to the ADC circuitry. In particular, the ADC testing circuitry may include reference voltage generation circuitry configured to generate reference voltages serving as test voltages for the ADC circuitry. The ADC circuitry may be coupled to a test input for receiving the test voltages via switching circuitry and may be coupled to a main data input for receiving system data via the switching circuitry. Testing may occur during an idling time period of the system and when the switching circuitry couples the test input to the ADC circuitry. Test input voltages corresponding to one or more stages in the ADC circuitry may be provided to the ADC circuitry, and corresponding output values from the ADC circuitry may be compared to an expected value and/or expected threshold values.

Techniques regarding error detection in one or more generated signals based on one or more signal-to-noise ratios are provided. For example, one or more embodiments described herein can include a system, which can include a memory that can store computer executable components. The system can also include a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can include a signal analysis component that can determine a signal-to-noise ratio associated with a generated signal, wherein the signal-to-noise ratio incorporates a signal value based on a reference signal and a noise value based on a difference between the reference signal and an acquired signal.

Body text indent—does not have paragraph numbering turned on. Not needed in the Abstract. An integrated circuit device includes a digital sine wave generator configured to produce portions of a digital sine wave, a combiner circuit configured to output each of the portions of the digital sine wave combined with a respective calibration code during operation in a post-production dynamic test mode, a digital to analog converter (DAC) configured to output an analog sine wave based on the output of the combiner circuit, and a test analog to digital converter (ADC) including an input terminal directly connected to the output of the DAC, and configured to generate a second digital sine wave based on the analog sine wave.

Input circuitry for an analog-to-digital converter (ADC) is provided. The input circuitry includes a calibration signal source configured to output a calibration signal for the ADC and an analog circuitry configured to receive and process an analog input signal for the ADC. The analog circuitry is further configured to generate a combined signal by combining the analog input signal and the calibration signal. The input circuitry further includes a buffer amplifier coupled to the analog circuitry and configured to supply a buffered signal to the ADC based on the combined signal. Further, the input circuitry includes neutralization circuitry configured to generate, based on the calibration signal, a neutralization signal for mitigating an unwanted signal component related to a limited reverse isolation of the analog circuitry. The neutralization circuitry is further configured to supply the neutralization signal to at least one of an input node and an intermediate node of the analog circuitry.

An electronic device may include an electronic display having multiple display pixels to display an image based on analog voltage signals. The electronic device may also include optical calibration circuitry to generate digital-to-analog converter (DAC) data based on image data associated with the image and dither circuitry to reduce a bit-depth of the DAC data, generating dithered DAC data. Additionally, the electronic device may include a gamma generator having one or more DACs to generate the analog voltage signals based on the dithered DAC data, which may instruct the gamma generator to generate the analog voltage signals indicative of the image data.