An image sensor chip includes an internal voltage generator for generating internal voltages using an external voltage received at a first terminal of the image sensor chip, a temperature sensor for generating a temperature voltage, a selection circuit for outputting one of the external voltage, the internal voltages, and the temperature voltage, a digital code generation circuit for generating a digital code using an output voltage of the selection circuit, and a second terminal for outputting the digital code from the image sensor chip.

An image sensor chip includes an internal voltage generator for generating internal voltages using an external voltage received at a first terminal of the image sensor chip, a temperature sensor for generating a temperature voltage, a selection circuit for outputting one of the external voltage, the internal voltages, and the temperature voltage, a digital code generation circuit for generating a digital code using an output voltage of the selection circuit, and a second terminal for outputting the digital code from the image sensor chip.

A smart watch according to the present invention comprises: a reception unit to which an analog speech signal is inputted; a first amplification unit for amplifying the analog speech signal; an A/D converter for converting the amplified analog speech signal into a digital speech signal; a control unit for receiving and outputting the digital speech signal outputted from the A/D converter and outputting a digital speech signal received and inputted through an antenna; an RF transceiver for controlling signals such that the signal received through the antenna is inputted to the control unit, and the signal outputted from the control unit is transmitted through the antenna; a D/A converter for converting the digital speech signal into an analog speech signal; a second amplification unit for amplifying the analog speech signal; and a speech output unit for outputting the analog speech signal outputted from the second amplification unit.

A smart watch according to the present invention comprises: a reception unit to which an analog speech signal is inputted; a first amplification unit for amplifying the analog speech signal; an A/D converter for converting the amplified analog speech signal into a digital speech signal; a control unit for receiving and outputting the digital speech signal outputted from the A/D converter and outputting a digital speech signal received and inputted through an antenna; an RF transceiver for controlling signals such that the signal received through the antenna is inputted to the control unit, and the signal outputted from the control unit is transmitted through the antenna; a D/A converter for converting the digital speech signal into an analog speech signal; a second amplification unit for amplifying the analog speech signal; and a speech output unit for outputting the analog speech signal outputted from the second amplification unit.

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation.

A light sensor circuit, which comprising a photodiode and a voltage follower. By setting the voltage follower to reduce the influence from the junction capacitance of the photodiode, a required time of a repeat integration module will not be influenced by the photodiode to efficiently keep the performance and the accuracy of the analog to digital converting device when the light sensor circuit is used to the analog to digital converting device in repeat operation.

A light sensor circuit, which comprising a photodiode and a voltage follower. By setting the voltage follower to reduce the influence from the junction capacitance of the photodiode, a required time of a repeat integration module will not be influenced by the photodiode to efficiently keep the performance and the accuracy of the analog to digital converting device when the light sensor circuit is used to the analog to digital converting device in repeat operation.

A peak current mode ‘PCM’ controller comprising control logic arranged to produce a series of digital control values derived from a voltage sense signal, control logic arranged to produce a digital slope compensation value, a first digital to analogue converter ‘DAC’ arranged to receive the series of digital control values and output a corresponding analogue control voltage, a second DAC arranged to receive the digital slope compensation value and output a corresponding analogue slope compensation voltage, an analogue differential integrator arranged to receive the analogue control voltage and the analogue slope compensation voltage, integrate the analogue slope compensation voltage, subtract the integrated slope compensation voltage from the analogue control voltage, and output the result of the subtraction as an analogue output voltage, a comparator arranged to compare the analogue output voltage to a voltage of an analogue current sense signal and produce an output signal when the analogue current sense signal voltage is equal to or exceeds the analogue output voltage, and control logic arranged to produce a drive signal in response to the output signal.

A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.