A merging unit including one or more input interfaces for receiving a plurality of input signals wherein one or more voltages and/or one or more currents measured by a plurality of measurement devices, digital processing means and one or more output interfaces for outputting an output signal. The digital processing means are configured to high-pass filter, using one or more digital filters, at least one of the plurality of input signals for lowering a time constant associated with the at least one of the one or more input signals to match a target time constant or for raising a high-pass cut-off frequency associated with the at least one of the one or more input signals to match a target high-pass cut-off frequency and to merge, following the high-pass filtering, the plurality of input signals into the output signal having a pre-defined output format.

The present disclosure relates to communication devices and provides a method and apparatus for calibrating a sampling timing skew between time-interleaved analog to digital converter (ADC) channels, a time-interleaved ADC, an electronic device, and a computer readable medium. The time-interleaved ADC includes multiple ADC channels. The method includes: calculating, for every two adjacent channels, a correlation value between digital signals of two adjacent channels, according to the digital signals output by every two adjacent channels; calculating a timing skew adjustment amount corresponding to a sampling timing skew of each of the channels relative to a reference channel according to the correlation value corresponding to every two adjacent channels, the reference channel being any designated channel among the plurality of channels; and calibrating the sampling timing skew of each of the channels relative to the reference channel according to the timing skew adjustment amount corresponding to each of the channels.

High speed, high dynamic range SAR ADC method and architecture. The SAR DAC comparison method can make fewer comparisons with less charge/fewer capacitors. The architecture makes use of a modified top plate switching (TPS) DAC technique and therefore achieves very high-speed operation. The present disclosure proffers a unique SAR ADC method of input and reference capacitor DAC switching. This benefits in higher dynamic range, no external decoupling capacitory requirement, wide common mode range and overall faster operation due to the absence of mini-ADC.

A light receiving unit receives a pulsed optical signal arriving from a search region. A branching unit generates, from a received light signal, a plurality of branch signals having signal intensities proportional to a signal intensity of the received light signal and different from one another. A conversion unit converts, from analog to digital, a signal fed via the individual path selected by a selection unit, and in accordance with a result of the conversion, a processing unit generates information regarding an object reflecting the optical signal. A control unit causes the selection unit to select one of the individual paths for which a determination unit determines that a magnitude of the fed signal is within an input range of the conversion unit and which provides the highest gain.

A light receiving unit receives a pulsed optical signal arriving from a search region. A branching unit generates, from a received light signal, a plurality of branch signals having signal intensities proportional to a signal intensity of the received light signal and different from one another. A conversion unit converts, from analog to digital, a signal fed via the individual path selected by a selection unit, and in accordance with a result of the conversion, a processing unit generates information regarding an object reflecting the optical signal. A control unit causes the selection unit to select one of the individual paths for which a determination unit determines that a magnitude of the fed signal is within an input range of the conversion unit and which provides the highest gain.

A method for differentiator-based compression of digital data includes (a) multiplying a tap-weight vector by an original data vector to generate a predicted signal, the original data vector comprising N sequential samples of an original signal, N being an integer greater than or equal to one, (b) using a subtraction module, subtracting the predicted signal from a sample of the original signal to obtain an error signal, (c) using a quantization module, quantizing the error signal to obtain a quantized error signal, and (d) updating the tap-weight vector according to changing statistical properties of the original signal.

In a solid-state imaging element that performs AD conversion for each pixel, image quality degradation when resolution is lowered is suppressed without wastefully consuming power. The solid-state imaging element includes a plurality of pixels. Each of the plurality of pixels is provided with a comparison unit, an addition circuit, and a data storage unit. The comparison unit generates a difference signal obtained by amplifying a difference between an analog pixel signal to which a predetermined coordinate is assigned and a predetermined reference signal. The addition circuit generates an addition signal by performing analog addition of the difference signal and a difference signal regarding another coordinate adjacent to the predetermined coordinate. The data storage unit holds a digital signal indicating a time when an output signal of the comparison unit corresponding to the addition signal is inverted.

A technique for generating analog waveforms includes combining a desired, in-band signal with a randomizing, out-of-band signal at an input of a DAC, operating the DAC to generate DAC output based on a combination of the desired signal and the randomizing signal, and filtering the DAC output to pass the desired signal while removing the randomizing signal.

A fingerprint sensing device that includes an analog-front-end (AFE) circuit, an analog-to-digital converter (ADC) and a correction circuit is introduced. The AFE circuit generates an image signal, and the ADC converts the image signal to an output digital code. The correction circuit receives a plurality of first output digital codes that are generated by performing a plurality of first fingerprint sensing operations in a plurality of first exposure time periods. The correction circuit is further configured to calculate a second exposure time period for a second fingerprint sensing operation according to the first output digital codes and the first exposure time periods, wherein the fingerprint sensing device performs the second fingerprint operation in the second exposure time period to generate a second output digital code.

A fingerprint sensing device that includes an analog-front-end (AFE) circuit, an analog-to-digital converter (ADC) and a correction circuit is introduced. The AFE circuit generates an image signal, and the ADC converts the image signal to an output digital code. The correction circuit receives a plurality of first output digital codes that are generated by performing a plurality of first fingerprint sensing operations in a plurality of first exposure time periods. The correction circuit is further configured to calculate a second exposure time period for a second fingerprint sensing operation according to the first output digital codes and the first exposure time periods, wherein the fingerprint sensing device performs the second fingerprint operation in the second exposure time period to generate a second output digital code.