Quantum repeater systems and apparatus for quantum communication. In one aspect, a system includes a quantum signal receiver configured to receive a quantum field signal; a quantum signal converter configured to: sample quantum analog signals from a quantum field signal received by the quantum signal receiver; encode sampled quantum analog signals as corresponding digital quantum information in one or more qudits, comprising applying a hybrid analog-digital encoding operation to each quantum analog signal and a qudit in an initial state; decode digital quantum information stored in the one or more qudits as a recovered quantum field signal, comprising applying a hybrid digital-analog decoding operation to each qudit and a quantum analog register in an initial state; a quantum memory comprising qudits and configured to store digital quantum information encoded by the quantum signal converter; and a quantum signal transmitter configured to transmit the recovered quantum field signal.

The present disclosure relates to a dual-clock generation circuit and method and an electronic device, and relates to the technical field of integrated circuits. The dual-clock generation circuit includes: a first inverter module, configured to access a first signal and output a first clock output signal; a second inverter module, configured to access a second signal and output a second clock output signal, where the first signal and the second signal are opposite clock signals; a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal.

Methods for use in a measurement system. Some embodiments comprise at least one sensor unit and a control unit, wherein the at least one sensor unit is configured to detect a physical quantity and to form a sensor data signal. The method comprises, at the control unit, receiving a data receive signal from the sensor unit, and interpreting the data receive signal to be one of at least the sensor data signal and another data signal, wherein the interpreting is based on an attribute information intrinsic to the data receive signal. Furthermore, there is a sensor unit for use in measurement data acquisition, an apparatus configured to control a measurement data acquisition, a measurement system for use in measurement data acquisition, and a medium incorporating a sequence of operation steps that, when executed, perform a method for use in a measurement system for data acquisition.

The present disclosure concerns an electronic device connected to an antenna. The electronic device delivers a first amplitude-modulated analog signal of a signal captured by the antenna, the capture signal associated with an electromagnetic field exhibiting intervals at a minimum level. The electronic device includes a first circuit, a second circuit, and a third circuit. The first circuit delivers a second analog signal by rectification and filters the first analog signal. The second circuit delivers a first binary signal based on the demodulation of the second analog signal. The third circuit couples the antenna to a resistor during each pause. The resistance value of the resistor depends on the maximum amplitude of the electromagnetic field before the pause.

Aspects of the technology described herein relate to control circuitry configured to turn on and off the ADC driver. In some embodiments, the control circuitry is configured to turn on and off the ADC driver in synchronization with sampling activity of an ADC, in particular based on when an ADC is sampling. The control circuitry may be configured to turn on the ADC driver during the hold phase of the ADC a time period before the track phase and to turn off the ADC driver during the hold phase a time period after the track phase. In some embodiments, the control circuitry is configured to control a duty cycle of the ADC driver turning on and off. In some embodiments, the control circuitry is configured to control a ratio between an off current and an on current in the ADC driver.

Apparatus includes an ADC configured to convert an analog signal to a digital signal, a comparator having a first input responsive to the analog signal, a second input responsive to the digital signal, and an output at which a comparison signal is provided, and an output checker configured to process the comparison signal to generate a fault signal indicative of whether a fault has occurred in the ADC. The comparator can be an analog comparator in which case the digital signal is converted to an analog signal for the comparison or a digital comparator in which case an additional ADC is provided to convert the analog signal into a digital signal for the comparison. Embodiments include more than one ADC in which case summation elements are provided to sum the analog signals and the digital signals for the comparison.

A method for demodulating an RF signal to polar in-phase and quadrature (IQ) components that includes converting an RF signal with an analog-to-digital converter and calculating the polar in-phase and quadrature (IQ) components of the RF signal as an IQ phasor phase angle and an IQ amplitude using a digital processor. The analog-to-digital converter uses a sampling rate, where, when the sampling rate used has sampling rates other than 3 times an RF carrier frequency of the RF signal, a digital logic circuit splines data to the sampling rate of 3 times the RF carrier frequency of the RF signal. The digital processor calculates the polar in-phase and quadrature (IQ) components of the RF signal as an IQ phasor phase angle and an IQ amplitude using addition, subtraction, multiplication, division, and absolute value.

According to one embodiment, an electronic circuit includes an oscillator and a measuring circuit. The oscillator generates a first signal with a frequency corresponding to a time. The measuring circuit measures a first voltage based on a resonance frequency in a terminal of a semiconductor device where the first signal is supplied.

In a solid-state imaging element equipped with per-column ADCs, noise is reduced. A test signal source generates a test signal of a predetermined level. An analog-to-digital converter increases/decreases an analog signal according to an analog gain selected from among a plurality of analog gains, and converts the increased/decreased analog signal to a digital signal. An input switching section inputs, as the analog signal, either a test signal or a pixel signal to the analog-to-digital converter. A correction value calculation section obtains, on the basis of the test signal and the digital signal, a correction value for correcting an error in the selected analog gain, and outputs the correction value. A correction section corrects the digital signal according to the outputted correction value.

A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.