An integrated circuit (IC) includes a current source device configured to generate a bias current. The IC also includes a comparator, a circuit, a memory, and a digital-to-analog circuit (DAC). The comparator has a first input, a second input, and a comparator output. The first input receives a reference voltage, and the second input receives a voltage indicative of a bias current through the IC. The circuit is coupled to the comparator output. The circuit iteratively generates a final trim code based on an output signal from the comparator. The memory stores the final trim code. The DAC controls a level of the bias current through the current source device based on the final trim code.

Radio frequency (RF) generators are disclosed. A RF generator may include a modulator configured to output a pulsed RF signal by modulating an RF carrier using a pulsed analog signal as a modulating signal. The modulating signal may be based on a file. The file may be received via a communication interface. The RF generator may further include an amplification stage configured to amplify the pulsed RF signal output by the modulator. RF generation systems and methods of generating a pulsed RF signal also disclosed.

Radio frequency (RF) generators are disclosed. A RF generator may include a modulator configured to output a pulsed RF signal by modulating an RF carrier using a pulsed analog signal as a modulating signal. The modulating signal may be based on a file. The file may be received via a communication interface. The RF generator may further include an amplification stage configured to amplify the pulsed RF signal output by the modulator. RF generation systems and methods of generating a pulsed RF signal also disclosed.

Radio frequency (RF) generators are disclosed. A RF generator may include an analog signal generator configured to generate a pulsed analog signal responsive to a digital pulsed waveform defined by one or more commands. The RF generator may also include a modulator configured to generate a pulsed radio frequency (RF) signal by modulating an RF carrier using the pulsed analog signal as a modulating signal. Further, the RF generator may include an amplification stage configured to amplify the pulsed RF signal output by the modulator. RF generation systems and methods of generating a pulsed RF signal also disclosed.

Radio frequency (RF) generators are disclosed. A RF generator may include an analog signal generator configured to generate a pulsed analog signal responsive to a digital pulsed waveform defined by one or more commands. The RF generator may also include a modulator configured to generate a pulsed radio frequency (RF) signal by modulating an RF carrier using the pulsed analog signal as a modulating signal. Further, the RF generator may include an amplification stage configured to amplify the pulsed RF signal output by the modulator. RF generation systems and methods of generating a pulsed RF signal also disclosed.

An integrated circuit is disclosed. The integrated circuit includes a first equalizer circuit and a second equalizer circuit. The first equalizer circuit is configured to equalize an input signal which is added by offset voltages that are different from each other, to generate output signals with voltage levels that are different from each other. The second equalizer circuit coupled to the first equalizer circuit. The second equalizer circuit includes a first equalizer unit and a second equalizer unit. The first equalizer unit is configured to equalize the output signals, to generate odd data signals. The second equalizer unit is coupled to the first equalizer unit and configured to equalize the output signals, to generate even data signals. A method is also disclosed herein.

An integrated circuit is disclosed. The integrated circuit includes a first equalizer circuit and a second equalizer circuit. The first equalizer circuit is configured to equalize an input signal which is added by offset voltages that are different from each other, to generate output signals with voltage levels that are different from each other. The second equalizer circuit coupled to the first equalizer circuit. The second equalizer circuit includes a first equalizer unit and a second equalizer unit. The first equalizer unit is configured to equalize the output signals, to generate odd data signals. The second equalizer unit is coupled to the first equalizer unit and configured to equalize the output signals, to generate even data signals. A method is also disclosed herein.

A detector circuit being part of a Radio Frequency Identification (RFID) device is provided, including: a bias current generator circuit configured to generate an output bias current that is proportional to the square of a temperature-dependent input current; first and second Field-Effect Transistor (FET) devices; at least one of the first and the second FET devices is biased by means of the output bias current of the bias current generator circuit so that FET device(s) operates in a sub-threshold region; an incoming Radio Frequency (RF) signal being coupled into at least one of the first and the second FET devices; a current source configured to generate a variable threshold current; and a comparator configured to determine, based on the variable threshold current and the incoming RF signal, whether a value of the incoming RF signal exceeds a threshold value.

According to one aspect of the invention, a method for making relatively high resolution measurements using relatively low resolution devices includes the steps of: deriving a first anticipated measurement value; using the first anticipated measurement value as an initial feed-forward signal; comparing the initial feed forward signal to a received signal from a sensor, thereby generating a compared signal; scaling the compared signal to full scale of an analog-to-digital converter, thereby generating a scaled signal; delivering the scaled signal in binary form for computation; and iteratively performing the comparing step until the compared signal is below a predetermined threshold value.

A integrated circuit device includes digital-to-analog converter (DAC) circuitry including a resistor DAC that includes a resistor-two-resistor DAC configured to receive a first sub-word that includes a most significant bit (MSB) of a digital input signal and to output an analog output signal representative of the first sub-word, a resistor ladder configured to receive the analog output signal and a second sub-word that includes an intermediate significant bit (ISB) of the digital input signal and to generate an analog interpolated signal. The resistor ladder includes a plurality of resistor elements connected in series with one another to define a plurality of tap nodes, wherein a respective tap node is arranged between every two adjacent ones of the resistor elements, and a switching circuit having plurality of switches, wherein each switch is configured to selectively connect a respective one of the tap nodes to an output of the resistor ladder to generate the analog interpolated signal.