Detector circuit for an RFID-device

Abstract

A detector circuit being part of a Radio Frequency Identification (RFID) device is provided, including: a bias current generator circuit configured to generate an output bias current that is proportional to the square of a temperature-dependent input current; first and second Field-Effect Transistor (FET) devices; at least one of the first and the second FET devices is biased by means of the output bias current of the bias current generator circuit so that FET device(s) operates in a sub-threshold region; an incoming Radio Frequency (RF) signal being coupled into at least one of the first and the second FET devices; a current source configured to generate a variable threshold current; and a comparator configured to determine, based on the variable threshold current and the incoming RF signal, whether a value of the incoming RF signal exceeds a threshold value.

Claims

1. A detector circuit being part of a Radio Frequency Identification (RFID) device, and comprising: a bias current generator circuit configured to generate an output bias current that is proportional to the square of a temperature-dependent input current; first and second Field-Effect Transistor (FET) devices; at least one of the first and the second FET devices being biased by means of the output bias current of the bias current generator circuit so that said at least one of the first and the second FET devices operates in a sub-threshold region; an incoming Radio Frequency (RF) signal being coupled into at least one of the first and the second FET devices; a current source configured to generate a variable threshold current; and a comparator configured to determine, based on the variable threshold current and the incoming RF signal, whether a value of the incoming RF signal exceeds a threshold value, wherein the first and the second FET devices are first and second n-channel metal-oxide-semiconductor (NMOS) transistors, wherein the bias current generator circuit comprises a band-gap generator, wherein each of a first NMOS transistor and a second NMOS transistor is diode-connected, wherein the first and the second NMOS transistors are connected in series, and wherein a third NMOS transistor is biased by a constant reference current.

2. The detector circuit according to claim 1, wherein the bias current generator circuit comprises five FET devices.

3. The detector circuit according to claim 2, wherein FET devices of the bias current generator circuit are n-channel metal-oxide-semiconductor (NMOS) transistors operating in the sub-threshold region.

4. The detector circuit according to claim 1, wherein the incoming RF signal is AC-coupled into the first NMOS transistor.

5. The detector circuit according to claim 1, further comprising a third NMOS transistor, arranged between the first NMOS transistor and a load device.

6. The detector circuit according to claim 5, the detector circuit further comprising a fourth NMOS transistor, arranged between the second NMOS transistor and the load device.

7. The detector circuit according to claim 6, wherein the current source configured to generate the variable threshold current is a current output digital-to-analogue converter (DAC) connected to the fourth NMOS transistor and to the load device.

8. The detector circuit according to claim 6, wherein the comparator configured to determine whether the value of the incoming RF signal exceeds the threshold value is connected to the fourth NMOS transistor and to the load device.

9. A detector circuit being part of a Radio Frequency Identification (RFID) device, and comprising: a bias current generator circuit configured to generate an output bias current that is proportional to the square of a temperature-dependent input current; first and second Field-Effect Transistor (FET) devices; at least one of the first and the second FET devices being biased by means of the output bias current of the bias current generator circuit so that said at least one of the first and the second FET devices operates in a sub-threshold region; an incoming Radio Frequency (RF) signal being coupled into at least one of the first and the second FET devices; a current source configured to generate a variable threshold current; and a comparator configured to determine, based on the variable threshold current and the incoming RF signal, whether a value of the incoming RF signal exceeds a threshold value, wherein the first and the second FET devices are first and second n-channel metal-oxide-semiconductor (NMOS) transistors, wherein the RF signal is alternately AC-coupled into the first and the second NMOS transistors and the first and the second FET devices are alternately biased by means of the output bias current of the bias current generator circuit so that the first and the second FET devices operate in the sub-threshold region.

10. The detector circuit according to claim 9, wherein a bias is applied on the first and the second NMOS transistors at the same time the first and the second NMOS transistors receive the RF signal.

11. The detector circuit according to claim 10, wherein current of a current output digital-to-analogue converter (DAC) is alternated into a first and a second load.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the following, a preferred embodiment of the invention will be described in a non-limiting and exemplary way by making reference to the drawings, in which:

(2) FIG. 1 schematically shows a block diagram of a detector circuit according to one embodiment of the present invention.

(3) FIG. 2 is a schematic block diagram of a bias current generator circuit usable in the detector circuit of FIG. 1.

(4) FIG. 3 schematically shows a block diagram of a detector circuit according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(5) Various embodiments are described hereinafter with reference to the Figures. It should be noted that elements of similar structures or functions are represented by like reference numerals throughout the Figures. It should also be noted that the Figures are only intended to facilitate the description of the embodiments. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. In addition, an illustrated embodiment needs not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular embodiment is not necessarily limited to that embodiment and can be practiced in any other embodiments even if not so illustrated, or if not so explicitly described.

(6) In FIG. 1 a block diagram of a detector circuit according to one embodiment of the present invention is schematically presented.

(7) In the following, the components and the operation of the detector circuit are discussed in greater detail.

(8) An energy source provides supply voltage V.sub.DD between 1.3 V and 2.0 V. A first and a second NMOS-transistors 11, 12 of the detector circuit 10 are biased in weak inversion by an output bias current. This output bias current is generated by a voltage from a bias current generator circuit 20 and compensates for temperature-sensitivity of the detector. The bias current generator circuit 20 will be more thoroughly discussed in connection with FIG. 2. A resistor 15 is connected from the bias current generator circuit 20 to the gate of the NMOS-transistor 11 to allow RF-signals to occur at the transistor gate without loading by the bias current generator 20.

(9) A third NMOS-transistor 13 is arranged between the first NMOS-transistor 11 and a load device 16 whereas a fourth NMOS transistor 14 is arranged between the second NMOS-transistor 12 and the load device 16. The third and the fourth NMOS-transistors 13, 14 are basically used as cascodes in order to isolate the first and the second NMOS-transistors 11, 12 from other electrical signals present in the detector circuit 10.

(10) An RF-signal is applied to a gate of the NMOS-transistor 11 through a capacitor 8. The capacitor 8 and the resistor 15 form a high-pass network that allows RF-signals to pass to the gate of the NMOS-transistor 11. The RF signal is added to the DC-level of the output bias current generator 20, said generator being connected to the first NMOS-transistor 11. As a consequence of the transistor sub-threshold operation non-linearity, the current flowing through the NMOS-transistor 11 is changed and increases with increasing RF-signal level. This current subsequently flows through the load device 16, resulting in a variable voltage being generated at the drain of the NMOS-transistor 13. In the shown embodiment, the load device 16 is a resistor but it could also be a conventional diode.

(11) The NMOS-transistor 12 is only affected by the voltage attributable to the voltage output of bias current generator 20. Accordingly, the drain current of the NMOS-transistor 12 is constant and generates a fixed voltage at the drain of the NMOS-transistor 14.

(12) A current output DAC (DACdigital-to-analogue converter) 18 is connected to the NMOS-transistor 14 and contributes in generating a threshold current bias. The DAC 18 is also connected to the load device 16. The voltage at the drain of the NMOS-transistor 14 so-to-say corresponds to the aggregate of the current generated by the NMOS-transistor 12 and the current output by the DAC 18. The voltage at the drain of the NMOS-transistor 14 is lower than the voltage at the drain of the NMOS-transistor 13 when no RF-signal is present.

(13) Here, when an increasing RF-signal is applied to the previously discussed coupling capacitor 8, an additional current will flow through the NMOS-transistors 11 and 13 and eventually the voltage at the drain of the NMOS-transistor 13 will become lower than the voltage at the drain of the NMOS-transistor 14.

(14) The detector circuit further comprises a conventional comparator 19 connected to the load device 16. Once the voltage at the drain of the NMOS-transistor 14 exceeds the voltage at the drain of the NMOS-transistor 13, the comparator 19 will signal that the signal detection threshold has been reached. The threshold detection level may then be reset by suitably adapting the current originating from the current output DAC 18.

(15) The solution shown in FIG. 1 is an energy-efficient power detector for incoming RF-signals. As previously discussed, the circuit at hand is suitable for implementation in RFID-applications and hence it complies with strict energy-efficiency requirementsits energy consumption is below 2 A at a voltage of 1.65 V.

(16) It is to be noted that the circuit needs to be operable in a rather limited signal power interval, ranging between 30 dBm and +15 dBm. Accordingly, the detectable RF-signals are in mW- and W-domain. Here and as customary in RF-applications, the unit of power level dBm (decibel-milliwatts) is used to designate the power of the incoming RF-signal relative to a 50-ohm impedance.

(17) Further, in the operating temperature range of 40 C. to +85 C. the detector as shown in FIG. 1 ensures a substantially flat response, i.e. the response varies no more than +/0.5 dB relative to the defined detector threshold power.

(18) As easily inferred from the above, the detector circuit 10 shown in FIG. 1 may be manufactured by readily-available, standard semi-conductor components for a cost-efficient production process.

(19) Additionally, the detector circuit functions as an OOK-demodulator (OOKon-off keying) as well. For example, in its intended application the detector is enabled 100% of the time looking for RF-signal activity. Once a signal having a value that is above the predetermined level is detected, the threshold is slightly reduced, whereupon the OOK-demodulation may be initiated.

(20) In FIG. 2 a schematic block diagram of a bias current generator circuit usable in the detector circuit according to FIG. 1 is shown.

(21) Proportional to absolute temperature (PTAT) current generator circuits are well known in the art. In the art, the biasing current of such a PTAT-current circuit should increase linearly with increasing temperature.

(22) Structurally, the shown circuit 20 comprises five NMOS-transistors 21-25. All of these NMOS-transistors operate in the sub-threshold region, i.e. in weak inversion. The circuit further comprises a band-gap generator that contributes in generation of a constant, temperature-invariant reference current I.sub.MREF. Each of a first and a second NMOS-transistors 21, 22 are diode-connected. The first and the second NMOS-transistors 21, 22 are even connected in series. A third NMOS-transistor 23 is biased by the constant reference current I.sub.MREF mentioned above. A fourth NMOS-transistor 24 generates the reference current I.sub.MREF, more thoroughly described below. In the shown embodiment, a fifth NMOS-transistor 25 is any one of the NMOS-transistors 11 or 12 of FIG. 1 so that a circuit output current I.sub.DET occurs in this transistor.

(23) In the following the operation of the circuit of FIG. 2 will be discussed in greater detail.

(24) Voltage V.sub.DD is supplied to the circuit 20. The PTAT-input current I.sub.PTAT is generated in a separate circuit via PMOS- and NMOS-transistors operating in the sub-threshold region to form a PTAT-voltage which is applied to a resistor to form the PTAT-current. As seen, the PTAT-input current I.sub.PTAT is fed to the NMOS-transistors 21 and 22. As disclosed above, each of the first and the second NMOS-transistors 21 and 22 are diode-connected and the first and the second NMOS-transistors 21, 22 are even connected in series. Consequently, NMOS-transistors 21, 22 each achieve a gate-source voltage, V.sub.PTAT that is a function of the natural logarithm of the PTAT-input current. The diode-connection of the respective NMOS-transistor 21, 22 makes the drain-source voltage equal to the gate-source voltage. Thus, the two gate voltages V.sub.PTAT associated with NMOS-transistors 21 and 22, respectively, are summed to result in a gate voltage at the NMOS-transistor 23 of twice the value of V.sub.PTAT, i.e. 2.Math.V.sub.PTAT.

(25) The NMOS-transistor 23 is biased by a constant, temperature-invariant reference current I.sub.MREF provided by the NMOS-transistor 24 and its gate-source voltage is then V.sub.MREF.

(26) Considering the above, the gate-source voltage associated with NMOS-transistor 25, or equivalently, any one of the input NMOS-transistors 11 and 12 of FIG. 1, is 2.Math.V.sub.PTAT subtracted by V.sub.MREF. Since all of the voltages are natural logarithms of the currents and all transistor-devices of the circuit 20 are assumed to be of the same dimensions, summing the voltages becomes equivalent to multiplying the currents. Similarly, subtracting the voltages is equivalent to dividing the currents. Thus the output current I.sub.DET, occurring at the NMOS-transistor 25, of the bias current generator circuit 20 is the square of the current I.sub.PTAT divided by the reference current I.sub.MREF. Hereby it is achieved that the output current I.sub.DET is proportional to the square of temperature.

(27) Conclusively, the inputs into the shown circuit 20 of FIG. 2 are the obtained PTAT-current and the constant reference current I.sub.MREF. The resulting output current I.sub.DET is the square of the PTAT-current divided by the constant reference current I.sub.MREF. The output current I.sub.DET is the bias current of the NMOS-transistors 11 and 12 of the detector circuit discussed in connection with FIG. 1.

(28) Above rationale is supported by the following equations:
Drain Current: I.sub.D=(W/L).Math.I.sub.S.Math.e.sup.[q.Math.VGS/(n.Math.k.Math.T)]
Gate Voltage: V.sub.GS=(n.Math.k.Math.T/q).Math.ln(L.Math.I.sub.D/(W.Math.I.sub.S))
Voltage Loop: V.sub.GS1+V.sub.GS2=V.sub.GS3+V.sub.GS5
(n.Math.k.Math.T/q).Math.ln(L.Math.I.sub.PTAT/(W.Math.I.sub.S))+(n.Math.k.Math.T/q).Math.ln(L.Math.I.sub.PTAT/(W.Math.I.sub.S))=(n.Math.k.Math.T/q).Math.ln(L.Math.I.sub.MREF/(W.Math.I.sub.S))+(n.Math.k.Math.T/q).Math.ln(L.Math.I.sub.DET/(W.Math.I.sub.S))
ln(L.Math.I.sub.PTAT/(W.Math.I.sub.S))+ln(L.Math.I.sub.PTAT/(W.Math.I.sub.S))=ln(L.Math.I.sub.MREF/(W.Math.I.sub.S))+ln(L.Math.I.sub.DET/(W.Math.I.sub.S))
2.Math.ln(L.Math.I.sub.PTAT/(W.Math.I.sub.S))ln(L.Math.I.sub.MREF/(W.Math.I.sub.S))=ln(L.Math.I.sub.DET/(W.Math.I.sub.S))
ln(L.Math.(I.sub.PTAT).sup.2/(W.Math.I.sub.S.Math.I.sub.MREF))=ln(L.Math.I.sub.DET/(W.Math.I.sub.S))
.fwdarw.L.Math.(I.sub.PTAT).sup.2/(W.Math.I.sub.S.Math.I.sub.MREF))=L.Math.I.sub.DET/(W.Math.I.sub.S)).fwdarw.(I.sub.PTAT).sup.2/I.sub.MREF=I.sub.DET

(29) FIG. 3 schematically shows a block diagram of the detector circuit according to another embodiment of the present invention. With reference to FIG. 3 and for the sake of brevity, the circuit components thoroughly described in conjunction with FIG. 1 are not further discussed.

(30) In FIG. 3 are switches which are enabled during one of two clock phases each defined as phase 1 or .sub.1 and phase 2 or .sub.2. .sub.1 and .sub.2 sequentially alternate, that is .sub.1 occurs first, then .sub.2, then .sub.1, followed by .sub.2 and the sequence continues as long as the circuit is enabled.

(31) As seen in FIG. 3, an RF-signal is alternately AC-coupled into the first and the second NMOS-transistors 11, 12 via capacitors 8, 9 during a first .sub.1 and a second .sub.2 phase, respectively. Simultaneously, the first and the second NMOS-transistors 11, 12 are continuously biased by means of the output voltage of the bias generator circuit 20 via resistors 15a and 15b, respectively. Once again, the NMOS-transistors 11, 12 operate in the sub-threshold region. Further, the output bias current is applied on one of the NMOS-transistors 11, 12 at the same time said NMOS-transistor receives the RF-signal. At the same time, current of the current output DAC 18 is alternated into loads (not shown) during the first .sub.1 and the second .sub.2 phase, respectively.

(32) Accordingly, the management of the incoming RF-signal is slightly modified compared to the embodiment of FIG. 1. As a result, the quantity of the available signals is doubled. Hence, a technique such as correlated double sampling (CDS) and subsequent signal subtraction may be used to eliminate undesired offset effects from the signal input stage. In this context, offset errors are due to errors between NMOS-transistors 11 and 12, errors between NMOS-transistors 13 and 14, errors between load resistors 16 and errors occurring within the comparator 19. Hereby, the total path from RF input to comparator input may be offset-corrected, thereby allowing signals smaller than the device offset levels to pass through to the detector output.

(33) In the drawings and the description, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.