A digital clock data recovery circuit including: a first vote circuit connected at an output of a first deserializer and configured to generate an even up/down signal based on even deserialized signals from the first deserializer; a first digital to analog converter (DAC) connected at an output of the first vote circuit and configured to control a voltage and/or frequency of a voltage controlled oscillator (VCO) based on the even up/down signal from the first vote circuit; a second vote circuit connected at an output of a second deserializer and configured to generate an odd up/down signal based on odd deserialized signals from the second deserializer; and a second DAC connected at an output of the second vote circuit and configured to control the voltage and/or frequency of the VCO based on the odd up/down signal from the second vote circuit.

A digital clock data recovery circuit including: a first vote circuit connected at an output of a first deserializer and configured to generate an even up/down signal based on even deserialized signals from the first deserializer; a first digital to analog converter (DAC) connected at an output of the first vote circuit and configured to control a voltage and/or frequency of a voltage controlled oscillator (VCO) based on the even up/down signal from the first vote circuit; a second vote circuit connected at an output of a second deserializer and configured to generate an odd up/down signal based on odd deserialized signals from the second deserializer; and a second DAC connected at an output of the second vote circuit and configured to control the voltage and/or frequency of the VCO based on the odd up/down signal from the second vote circuit.

The present invention corresponds to a method and a circuit for compensating the offset voltage of electronic circuits, where the circuit implementing the method comprises: a dynamic comparator (1); a phase detector (6) connected to the dynamic comparator (1), the phase detector (6); a finite-state machine (9) connected to the phase detector (4), a first digital-analog converter (12) connected to an output of the finite-state machine (9); a second digital-analog converter (13) connected to another output (11) of the finite-state machine (9); a polarization block (14) with a first input (15) connected to the output of the first digital-analog converter (12) and a second input (16) connected to the output of the second digital-analog converter (13); where the polarization block (14) polarizes an electronic circuit (17) and the dynamic comparator (1), the phase detector (6), and the finite-state machine (9) are connected to a clock signal (3). The method is characterized by the following steps: a) connecting a dynamic comparator to the output of the electronic circuit; b) measuring the phase change of the dynamic comparator outputs of step a by means of a phase detector; c) controlling the output signals of a finite-state machine according to the phase detector output of step b, which can be coded forward, backward or in phase; c) converting the output of the finite-state machine of step c to an analog signal using two digital-analog converters; d) connecting the output of the two digital-analog converters of step d to the control terminal of the electronic circuit polarization block; and, e) modifying the polarization current of the electronic circuit polarization block by means of the output signals of the two digital-analog converters connected in step e.

The present invention corresponds to a method and a circuit for compensating the offset voltage of electronic circuits, where the circuit implementing the method comprises: a dynamic comparator (1); a phase detector (6) connected to the dynamic comparator (1), the phase detector (6); a finite-state machine (9) connected to the phase detector (4), a first digital-analog converter (12) connected to an output of the finite-state machine (9); a second digital-analog converter (13) connected to another output (11) of the finite-state machine (9); a polarization block (14) with a first input (15) connected to the output of the first digital-analog converter (12) and a second input (16) connected to the output of the second digital-analog converter (13); where the polarization block (14) polarizes an electronic circuit (17) and the dynamic comparator (1), the phase detector (6), and the finite-state machine (9) are connected to a clock signal (3). The method is characterized by the following steps: a) connecting a dynamic comparator to the output of the electronic circuit; b) measuring the phase change of the dynamic comparator outputs of step a by means of a phase detector; c) controlling the output signals of a finite-state machine according to the phase detector output of step b, which can be coded forward, backward or in phase; c) converting the output of the finite-state machine of step c to an analog signal using two digital-analog converters; d) connecting the output of the two digital-analog converters of step d to the control terminal of the electronic circuit polarization block; and, e) modifying the polarization current of the electronic circuit polarization block by means of the output signals of the two digital-analog converters connected in step e.

A semiconductor device in which variations are controlled is provided. The semiconductor device has a function of converting a digital signal into an analog signal, and includes a digital-analog converter circuit, an amplifier circuit, first to fourth switches, a first output terminal, a second output terminal, and a power source. The amplifier circuit is configured to perform feedback control when the first switch and the fourth switch are on and the second switch and the third switch are off. The amplifier circuit is configured to perform comparison control when the first switch and the fourth switch are off and the second switch and the third switch are on; utilizing this, variations in the digital-analog converter circuit and the amplifier circuit are controlled.

A semiconductor device in which variations are controlled is provided. The semiconductor device has a function of converting a digital signal into an analog signal, and includes a digital-analog converter circuit, an amplifier circuit, first to fourth switches, a first output terminal, a second output terminal, and a power source. The amplifier circuit is configured to perform feedback control when the first switch and the fourth switch are on and the second switch and the third switch are off. The amplifier circuit is configured to perform comparison control when the first switch and the fourth switch are off and the second switch and the third switch are on; utilizing this, variations in the digital-analog converter circuit and the amplifier circuit are controlled.

Analog multipliers circuits can provide signal processing asynchronously and clock free and with low power consumptions, which can be advantageous, including in emerging mobile, portable, and at edge or near sensor artificial intelligence (AI) and machine learning (ML) applications. As such, analog multipliers can process signals memory-free in AI and ML applications, which avoids the power consumption and latency delays attributed to memory read-write cycles in conventional AI and ML digital processors. Based on standard digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of multi-quadrant current-mode analog multiplier (iMULT) circuits that can be utilized in current-mode multiply-accumulate (iMAC) circuits and artificial neural network (ANN) end-applications that require high-volumes, low costs, medium precision, low power consumptions, and clock free asynchronous signal processing.

A method and associated system have been proposed to achieve power savings in PWM DACs by truncating PWM sequences and maximizing the amount of time available to power up a DAC cell without sacrificing sensitivity to element mismatch. The DAC circuit includes a driver to receive a digital input and to provide a plurality of drive sequences, a digital-to-analog converter, and a controller. The digital-to-analog converter includes an array of digital-to-analog elements operable over several time steps. Upon identifying that the digital signal is below a threshold value, the controller is configured to shorten the drive sequences; and for each time step to identify a first set of elements and a second set of elements among the array of digital-to-analog elements; to apply the shortened drive sequences to the first set; to disable the second set; and to shift the first set and the second set by one element.

A method and associated system have been proposed to achieve power savings in PWM DACs by truncating PWM sequences and maximizing the amount of time available to power up a DAC cell without sacrificing sensitivity to element mismatch. The DAC circuit includes a driver to receive a digital input and to provide a plurality of drive sequences, a digital-to-analog converter, and a controller. The digital-to-analog converter includes an array of digital-to-analog elements operable over several time steps. Upon identifying that the digital signal is below a threshold value, the controller is configured to shorten the drive sequences; and for each time step to identify a first set of elements and a second set of elements among the array of digital-to-analog elements; to apply the shortened drive sequences to the first set; to disable the second set; and to shift the first set and the second set by one element.

A digital to analog converter that includes a delta sigma modulator coupled to receive a digital data. The delta sigma modulator supplies a multi-bit resistor digital to analog converter (DAC). The multi-bit resistor digital to analog converter supplies an amplifier with an analog signal corresponding to the digital data. A first low pass filter is coupled between the multi-bit digital to analog converter and the amplifier stage and filters out shaped quantization noise before it reaches the amplifier. A second low pass filter is coupled to an output of the amplifier stage and filters out residual quantization noise and chopping artifacts from the amplifier stage.