A digital to analog converter receives a digital input consisting of first least significant bits, second most significant bits, and third middle significant bits. The digital to analog converter includes first, second, and third sub-DACs. The first sub-DAC receives the first least significant bits, and includes first resistors each contributing a respective voltage, to provide a first output. The second sub-DAC receives the second most significant bits, and includes second resistors each contributing a respective voltage, to provide a second output as an output of the digital to analog converter. The third sub-DAC is connected to the first sub-DAC to receive the first output, and receives the third middle significant bits, and includes third resistors each contributing a respective voltage, to provide a third output to the second sub-DAC. The first and third resistors each has a physical area less than an area of each second resistor.

A digital to analog converter receives a digital input consisting of first least significant bits, second most significant bits, and third middle significant bits. The digital to analog converter includes first, second, and third sub-DACs. The first sub-DAC receives the first least significant bits, and includes first resistors each contributing a respective voltage, to provide a first output. The second sub-DAC receives the second most significant bits, and includes second resistors each contributing a respective voltage, to provide a second output as an output of the digital to analog converter. The third sub-DAC is connected to the first sub-DAC to receive the first output, and receives the third middle significant bits, and includes third resistors each contributing a respective voltage, to provide a third output to the second sub-DAC. The first and third resistors each has a physical area less than an area of each second resistor.

A semiconductor device in which an increase of circuit area is prevented is provided. A semiconductor device including a control circuit with a plurality of scan chain circuits, a DA converter electrically connected to the control circuit, and a plurality of potential holding units electrically connected to the DA converter is provided. The plurality of potential holding units each include a transistor including an oxide semiconductor in a channel formation region and a capacitor electrically connected to the transistor. In accordance with digital data held in any one of the plurality of scan chain circuits, an output potential output from the DA converter is held in any one of the plurality of potential holding units.

A semiconductor device in which an increase of circuit area is prevented is provided. A semiconductor device including a control circuit with a plurality of scan chain circuits, a DA converter electrically connected to the control circuit, and a plurality of potential holding units electrically connected to the DA converter is provided. The plurality of potential holding units each include a transistor including an oxide semiconductor in a channel formation region and a capacitor electrically connected to the transistor. In accordance with digital data held in any one of the plurality of scan chain circuits, an output potential output from the DA converter is held in any one of the plurality of potential holding units.

The present invention provides a heater temperature control circuit including a heater and a control circuit that controls a temperature of the heater, wherein the control circuit includes a bridge circuit in which a first circuit and a second circuit are connected in parallel, and an operational amplifier connected to the bridge circuit, wherein in the first circuit, the heater and a resistor are connected in series, and a midpoint of the first circuit is connected to one input portion of the operational amplifier, and an output value V.sub.out from the second circuit is input to the other input portion of the operational amplifier, the output value V.sub.out being obtained by multiplying a division ratio of a target resistance value R.sub.h of the heater and a resistance value R.sub.1 of the resistor with a reference voltage V.sub.ref of the bridge circuit.

An amplifier circuit may include an isolated amplifier circuit, disposed on a high voltage side of the amplifier circuit, and arranged to generate an isolated output signal. The amplifier circuit may include a first optocoupler circuit, disposed to receive the isolated output signal from the isolated amplifier circuit and an output amplifier circuit, disposed on a low voltage side of the amplifier circuit, and coupled to receive an optical output signal from the optocoupler circuit. The amplifier circuit may also include a calibration circuit, coupled to the output amplifier circuit, to generate a calibration initiation signal, and a second optocoupler circuit, disposed to receive the calibration initiation signal, and to output a switch signal, wherein a reference voltage is output to the isolated amplifier circuit.

An amplifier circuit may include an isolated amplifier circuit, disposed on a high voltage side of the amplifier circuit, and arranged to generate an isolated output signal. The amplifier circuit may include a first optocoupler circuit, disposed to receive the isolated output signal from the isolated amplifier circuit and an output amplifier circuit, disposed on a low voltage side of the amplifier circuit, and coupled to receive an optical output signal from the optocoupler circuit. The amplifier circuit may also include a calibration circuit, coupled to the output amplifier circuit, to generate a calibration initiation signal, and a second optocoupler circuit, disposed to receive the calibration initiation signal, and to output a switch signal, wherein a reference voltage is output to the isolated amplifier circuit.

The present invention includes: a first decoder that outputs mutually different two voltages as first and second selection voltages based on a first bit group of a digital data signal in a first selection state, and outputs one or both of the two voltages as the first and the second selection voltages in a second selection state; a second decoder that outputs mutually different two voltages as third and fourth selection voltages based on a second bit group of the digital data signal in the first selection state and outputs one voltage based on the second bit group as the third and the fourth selection voltages in the second selection state; and an amplifier circuit that averages a combination of the first and the second selection voltages or the third and the fourth selection voltages with predetermined weighting ratios and outputs the averaged voltage.

The present invention includes: a first decoder that outputs mutually different two voltages as first and second selection voltages based on a first bit group of a digital data signal in a first selection state, and outputs one or both of the two voltages as the first and the second selection voltages in a second selection state; a second decoder that outputs mutually different two voltages as third and fourth selection voltages based on a second bit group of the digital data signal in the first selection state and outputs one voltage based on the second bit group as the third and the fourth selection voltages in the second selection state; and an amplifier circuit that averages a combination of the first and the second selection voltages or the third and the fourth selection voltages with predetermined weighting ratios and outputs the averaged voltage.

Systems for monitoring or control can include reconfigurable input and output channels. Such reconfigurable channels can include as few as a single terminal and a ground pin, or such channels can include three or four terminal configuration such as for use in four-terminal resistance measurements. Channel reconfiguration can be accomplished such as using software-enabled or firmware-enabled control of channel hardware. Such channel hardware can include analog-to-digital and digital-to-analog conversion capability, including use of a digital-to-analog converter to provide field power or biasing. In an example, compensation can be provided to suppress a leakage current from flowing through a digital output to a load connected to the reconfigurable channel terminal, particularly when the digital output is disabled.