In accordance with an embodiment, a method of monitoring a data converter includes determining a multiplicity of time-associated linearity parameters that describe a linearity of the data converter at a multiplicity of different times, and determining a state of the data converter based on comparing at least one linearity parameter of the multiplicity of time-associated linearity parameters with a comparison parameter.

This disclosure describes techniques for performing computational operations on input unary bit streams using one or more scaling networks. In some examples, a device is configured to perform a digital computational operation, where the device includes a plurality of input wires and a plurality of output wires. Each input wire is configured to receive a respective input bit of an encoded input value, and each output wire is configured to output a respective output bit of an encoded output value. The device also includes scaling network circuitry configured to apply a function to the encoded input value by electrically routing at least one input wire of the plurality of input wires to at least two output wires of the plurality of output wires. The device can also include hybrid binary/unary computations.

A digital-to-analog conversion circuit (DAC) is operable to convert an input digital signal to an output analog signal. The DAC includes a digital signal processing circuit operable to process the input digital signal according to a first transfer function to generate a first processed digital signal and process the digital input signal according to a second transfer function to generate a second processed digital signal. The DAC includes a first unit DAC operable to convert the first processed digital signal to a first intermediate analog signal, and a second unit DAC operable to convert the second processed digital signal to a second intermediate analog signal. The DAC includes switching circuits and a combiner circuit to generate the output analog signal from the intermediate analog signals.

A digital-to-analog conversion circuit (DAC) is operable to convert an input digital signal to an output analog signal. The DAC includes a digital signal processing circuit operable to process the input digital signal according to a first transfer function to generate a first processed digital signal and process the digital input signal according to a second transfer function to generate a second processed digital signal. The DAC includes a first unit DAC operable to convert the first processed digital signal to a first intermediate analog signal, and a second unit DAC operable to convert the second processed digital signal to a second intermediate analog signal. The DAC includes switching circuits and a combiner circuit to generate the output analog signal from the intermediate analog signals.

A switch interface adapter allowing a simple open/close switch to be adapted to a digital and analog diagnostic switch interface includes: at least one coil having a first terminal and a second terminal, wherein the switch is electrically connected to the first terminal or the second terminal, and the at least one coil is activated or deactivated via the switch; a first contact switch comprising a digital line, wherein the at least one coil controls opening and closing of the first contact switch to break and complete the digital line respectively, the digital line is electrically connected to the ECU, and a digital signal is generated from the digital line as a digital input for the ECU; a second contact switch comprising an analog line, wherein the at least one coil controls opening and closing of the second contact switch to break and complete the analog line respectively, the analog line is electrically connected to the ECU, an analog signal is generated from the analog line as an analog input for the ECU, and the digital line comprises a first resistor serially connected to the second contact switch; and a second resistor comprising the analog line, wherein the second resistor is parallel disposed across the first resistor and the second contact switch. The ECU compares the digital input and the analog input to diagnose the switch interface.

A switch interface adapter allowing a simple open/close switch to be adapted to a digital and analog diagnostic switch interface includes: at least one coil having a first terminal and a second terminal, wherein the switch is electrically connected to the first terminal or the second terminal, and the at least one coil is activated or deactivated via the switch; a first contact switch comprising a digital line, wherein the at least one coil controls opening and closing of the first contact switch to break and complete the digital line respectively, the digital line is electrically connected to the ECU, and a digital signal is generated from the digital line as a digital input for the ECU; a second contact switch comprising an analog line, wherein the at least one coil controls opening and closing of the second contact switch to break and complete the analog line respectively, the analog line is electrically connected to the ECU, an analog signal is generated from the analog line as an analog input for the ECU, and the digital line comprises a first resistor serially connected to the second contact switch; and a second resistor comprising the analog line, wherein the second resistor is parallel disposed across the first resistor and the second contact switch. The ECU compares the digital input and the analog input to diagnose the switch interface.

Disclosed is a harmonic compensation device capable of effectively reducing the harmonic distortion of an analog output signal. The harmonic compensation device includes a harmonic compensator, a mixer, a digital-to-analog converter, and an analog output circuit. The harmonic compensator is configured to generate a digital compensation signal according to a digital input signal, in which the digital compensation signal includes the harmonic components of the digital input signal. The mixer is configured to generate a digital output signal according to the digital input signal and the digital compensation signal. The digital-to-analog converter is configured to generate an analog input signal according to the digital output signal. The analog output circuit is configured to generate an analog output signal according to the analog input signal.

Disclosed is a harmonic compensation device capable of effectively reducing the harmonic distortion of an analog output signal. The harmonic compensation device includes a harmonic compensator, a mixer, a digital-to-analog converter, and an analog output circuit. The harmonic compensator is configured to generate a digital compensation signal according to a digital input signal, in which the digital compensation signal includes the harmonic components of the digital input signal. The mixer is configured to generate a digital output signal according to the digital input signal and the digital compensation signal. The digital-to-analog converter is configured to generate an analog input signal according to the digital output signal. The analog output circuit is configured to generate an analog output signal according to the analog input signal.

An output buffer of a super source follower for driving a reference ramp signal of a column-parallel single slope type ADC of a solid-state imaging device is made as a class AB feedback configuration for controlling a feedback variable current source with a signal obtained by amplifying a current fluctuation flowing through an amplification transistor by an amplifier, and thereby, the upper limit of the drain voltage of the amplification transistor is not limited by the voltage between the gate and the source of the feedback variable current source.

An output buffer of a super source follower for driving a reference ramp signal of a column-parallel single slope type ADC of a solid-state imaging device is made as a class AB feedback configuration for controlling a feedback variable current source with a signal obtained by amplifying a current fluctuation flowing through an amplification transistor by an amplifier, and thereby, the upper limit of the drain voltage of the amplification transistor is not limited by the voltage between the gate and the source of the feedback variable current source.