In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.

In an example, a device comprises a first resistor coupled to a second resistor and to a trim resistor, the second resistor and the trim resistor coupled to a port configured to couple to a third resistor. The device also comprises a comparator having an inverting input coupled to a first node between the second resistor and the port and a non-inverting input coupled to a second node between the first resistor and the trim resistor. The device further includes a trim control circuit coupled to an output of the comparator and having an output coupled to the trim resistor, the trim control circuit configured to couple to multiple integrated trim resistors external to the device.

A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry includes first and second DAC circuits which generate first and second signals according to an input pattern. The input pattern includes at least one of first logic value and at least one of second logic value that have different numbers. The calibration circuitry performs a calibration operation according to first and second comparison results, to generate a control signal for controlling the second DAC circuit. The first comparison results are comparison results of the first and the second signals when the input pattern is a first pattern, the second comparison results are comparison results of the first and the second signals when the input pattern is a second pattern, and the first pattern is inverse to the second pattern.

Provided is an integrated circuit including an analog-to-digital converter (ADC) configured to convert an analog signal to a digital signal; and a digital signal processor (DSP) configured to process the digital signal, wherein the ADC generates a power source during a process for converting the analog signal into the digital signal and supplies power to the DSP through the power source.

A method for arranging a current source array of a DAC and a layout of a common-source current source array are provided in embodiments of the present disclosure for improving linearity and related performance of the DAC. The method includes, determining a number R of rows and a number C of columns of a common-source current source array; dividing the common-source current source array into M sub-arrays; segmenting the DAC to obtain (2.sup.X1) groups of thermometer encoding current sources and Y groups of binary encoding current sources; arranging the (2.sup.X1) groups of the thermometer encoding current sources into the M sub-arrays, arranging Y groups of binary encoding current sources into the M sub-arrays based on a number of binary encoding current sources in each of Y groups; arranging bias current sources evenly into the common-source current source array; and arranging other current sources as dummy cells.

An optical network includes a transmitting portion configured to (i) encode an input digitized sequence of data samples into a quantized sequence of data samples having a first number of digits per sample, (ii) map the quantized sequence of data samples into a compressed sequence of data samples having a second number of digits per sample, the second number being lower than the first number, and (iii) modulate the compressed sequence of data samples and transmit the modulated sequence over a digital optical link. The optical network further includes a receiving portion configured to (i) receive and demodulate the modulated sequence from the digital optical link, (ii) map the demodulated sequence from the second number of digits per sample into a decompressed sequence having the first number of digits per sample, and (iii) decode the decompressed sequence.

An apparatus that is comprised of a controller, a digital-to-analog converter (DAC), a temperature sensor, an analog-to-digital converter (ADC), and a voltage controlled oscillator (VCO). The controller to reads temperature data proportional to a temperature of the VCO, reads previously-calculated calibration data based on the read temperature data, determines a frequency command signal based on the read previously-calculated calibration data, and outputs the frequency command signal. The DAC converts the frequency command signal into a frequency analog signal. The temperature sensor produces the temperature signal. The ADC converts the temperature signal into the temperature data. The VCO produces an output frequency based on the frequency analog signal.

An apparatus that is comprised of a controller, a digital-to-analog converter (DAC), a temperature sensor, an analog-to-digital converter (ADC), and a voltage controlled oscillator (VCO). The controller to reads temperature data proportional to a temperature of the VCO, reads previously-calculated calibration data based on the read temperature data, determines a frequency command signal based on the read previously-calculated calibration data, and outputs the frequency command signal. The DAC converts the frequency command signal into a frequency analog signal. The temperature sensor produces the temperature signal. The ADC converts the temperature signal into the temperature data. The VCO produces an output frequency based on the frequency analog signal.

An integrated circuit device is disclosed. The integrated circuit device includes a capacitor array, a decoder circuit, and an integrated circuit. The capacitor array includes a plurality of capacitor units. The decoder circuit is coupled to the capacitor array. The integrated circuit is coupled to the decoder circuit. The decoder circuit is configured to conduct part of the plurality of capacitor units, and to un-conduct part of the plurality of capacitor units, so as to adjust a capacitance value coupled to the integrated circuit.

A sensor device includes at least one sensor, a digital signal processor and an amplifier. The at least one sensor is configured to measure a variable physical quantity and provide a raw sensor signal at an output of the at least one sensor. The digital signal processor is configured to preprocess the raw sensor signal output by the at least one sensor into a sensor signal and to further process the sensor signal into a pulse-width-modulated output signal having a duty cycle that is dependent on the measured quantity using a plurality of device-specific correction parameters stored in a memory to convert the sensor signal into the pulse-width modulated output signal. The amplifier is configured to convert the pulse-width modulated output signal into an analog voltage or current signal.