A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.

A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.

A neural network circuit includes: multiple storage portions that include a memristor; multiple D/A converters that receive data, causing a signal voltage to be applied to multiple voltage input terminals of the storage portions; multiple drive amplifiers that are connected between to the D/A converters and the voltage input terminals; multiple I/V conversion amplifiers that are connected to at least one current output terminal of the storage portions; multiple A/D converters; and a series circuit of a first switch and a second switch that is disposed in a feedback loop of each of the drive amplifiers; and a series circuit of a third switch and a fourth switch that is disposed in a feedback loop of each of the I/V conversion amplifiers.

A neural network circuit includes: multiple storage portions that include a memristor; multiple D/A converters that receive data, causing a signal voltage to be applied to multiple voltage input terminals of the storage portions; multiple drive amplifiers that are connected between to the D/A converters and the voltage input terminals; multiple I/V conversion amplifiers that are connected to at least one current output terminal of the storage portions; multiple A/D converters; and a series circuit of a first switch and a second switch that is disposed in a feedback loop of each of the drive amplifiers; and a series circuit of a third switch and a fourth switch that is disposed in a feedback loop of each of the I/V conversion amplifiers.

A method for simulating and optimizing a digital to analog converter is disclosed. The method may include receiving a plurality of digital words. The method may also include determining an effective number of bits, a respective amplitude and a first amplitude correction amount for each digital word. Further, the first amplitude correction amount may be applied to each respective amplitude to generate respective first corrected amplitudes. A timing uncertainty may be determined which may be used to determine a second amplitude correction for each digital word. The second amplitude correction may be applied to each of the respective first corrected amplitudes to generate respective second corrected amplitudes. Next, a representation of an analog signal may be generated based in part on the second corrected amplitudes. Finally, a filter may be applied to the representation of the analog signal and then the representation of the analog signal is outputted.

Methods, apparatus, systems and articles of manufacture for wideband and fast chirp generation for radar systems are disclosed herein. An example apparatus includes a phase digital-to-analog converter to convert a digital input that specifies at least one of a phase modulation or a frequency modulation into an analog output, and to generate a phase modulated output centered on an intermediate frequency. The example apparatus also includes a frequency multiplier to frequency multiply the phase modulated output centered on the intermediate frequency by a multiplication factor to generate a chirp signal.

Certain aspects of the present disclosure are directed to a digital predistortion (DPD) device for use within a wireless transmitter that permits the use of a downstream digital-to-analog converter that operates at a clock rate close to the bandwidth of a digital baseband input signal. In some examples, a sampling rate of a digital baseband input signal is increased using an upsampler to obtain an increased rate digital input signal. Predistortion is applied to the increased rate digital input signal using a DPD device to obtain a predistorted digital signal. The sampling rate of the predistorted digital signal is then decreased using a downsampler to obtain a lower-rate predistorted digital signal with a sampling rate below the increased rate of the upsampler (e.g. close to the bandwidth of a digital baseband input signal). A low pass filter may be provided to filter out-of-band signal components from the predistorted digital signal.

Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may include at least two processing paths, each including at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may include adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.

A mapping circuit (300) for selecting cells of a multi core hybrid I/Q digital to analog converter includes a first sub-mapping circuit (310a) configured to define a first group of cores for each data symbol to be transmitted and to select cells of the first group of cores for an I-code of the data symbol to be transmitted. The mapping circuit (310b) further includes a second sub-mapping circuit configured to define a second group of cores for each data symbol and to select cells of the second group of cores for a Q-code of the data symbol.

An apparatus for detecting a neural spike includes: a preprocessing circuit configured to remove a low-frequency component from a neural signal to form a low-frequency component removed neural signal, and amplify the low-frequency component removed neural signal; a comparing circuit configured to compare an output signal of the preprocessing circuit to a threshold signal; a merging circuit configured to merge spikes within a reference interval of an output signal of the comparing circuit into one peak, and to generate, based on the merging of the spikes, an output signal comprising pulses; and a counting circuit configured to count the pulses.