A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

Clock distribution circuitry comprising: a plurality of first buffers and second buffers, the first and second buffers being inverting buffers; and control circuitry configured to generate first, second, third and fourth control signals for bulk-voltage control of transistors of the buffers, the control circuitry configured to control at least one of the first to fourth control signals as a variable signal.

An apparatus includes a switched-capacitor filter. The switched-capacitor filter includes an integrator and a feedback loop between an output node of the integrator and an input node of the integrator, wherein the feedback loop includes a feedback capacitor, a first switch, and a second switch. The switched-capacitor filter also includes a pre-charge path between the output node of the integrator and the feedback capacitor, wherein the pre-charge path includes a pre-charge buffer and a third switch.

A vector sum circuit and a phase controller including the vector sum circuit are provided. The vector sum circuit includes an amplifier configured to amplify an input orthogonal signal by using a first metal oxide semiconductor field effect transistor (MOSFET), and a self body-biasing circuit comprising a resistor. The self body-biasing circuit is configured to connect a drain and a body of the first MOSFET to reduce a voltage connected to the body as a current at the drain increases.

A vector sum circuit and a phase controller including the vector sum circuit are provided. The vector sum circuit includes an amplifier configured to amplify an input orthogonal signal by using a first metal oxide semiconductor field effect transistor (MOSFET), and a self body-biasing circuit comprising a resistor. The self body-biasing circuit is configured to connect a drain and a body of the first MOSFET to reduce a voltage connected to the body as a current at the drain increases.

An electronic device for preventing or reducing damage to a radio frequency front end (RFFE). The electronic device including a memory device configured to store operating state information of a RFFE and a damage prevention condition of the RFFE, the RFFE providing a signal path for delivering a first transmission (TX) signal to an antenna, and a TX signal controller configured to generate a TX signal control signal in response to determining that the operating state information does not satisfy the damage prevention condition, the TX signal control signal causing the first TX signal to be blocked or a magnitude of the first TX signal to be reduced.

An electronic device for preventing or reducing damage to a radio frequency front end (RFFE). The electronic device including a memory device configured to store operating state information of a RFFE and a damage prevention condition of the RFFE, the RFFE providing a signal path for delivering a first transmission (TX) signal to an antenna, and a TX signal controller configured to generate a TX signal control signal in response to determining that the operating state information does not satisfy the damage prevention condition, the TX signal control signal causing the first TX signal to be blocked or a magnitude of the first TX signal to be reduced.

It is provided a signal processing system, comprising at least a first, a second and a third digital-to-analog converter (DAC); a processing unit configured for splitting a sampled signal into a first and a second signal corresponding to different frequency portions of the sampled signal, transmitting the first signal to the first DAC, splitting the second signal into a first and a second subsignal and transmitting the first subsignal to the second DAC and the second subsignal to the third DAC, the first subsignal corresponding to the real part of the second signal and the second subsignal corresponding to the imaginary part of the second signal; an IQ mixer configured for mixing an analog output signal of the second DAC and an analog output signal of the third DAC and a combiner for combining an analog output signal of the first DAC and an output signal of the IQ mixer.