An integrated circuit includes a functional circuit and a power calibration and monitoring system including a digital-to-analog converter (DAC), a variable gain amplifier (VGA), and a counter. The DAC generates a differential pair of feedback currents based on a digital count. The VGA generates a differential pair of amplified signals based on a magnitude difference between the differential pair of feedback currents and a differential pair of detection currents derived from a differential pair of node voltages associated with the functional circuit. The counter generates the digital count based on the differential pair of amplified signals. The differential pair of feedback currents is controlled such that the magnitude difference between the differential pair of detection currents and the differential pair of feedback currents is within a tolerance limit. A power associated with the functional circuit is calibrated and monitored based on the digital count.

An integrated circuit includes a functional circuit and a power calibration and monitoring system including a digital-to-analog converter (DAC), a variable gain amplifier (VGA), and a counter. The DAC generates a differential pair of feedback currents based on a digital count. The VGA generates a differential pair of amplified signals based on a magnitude difference between the differential pair of feedback currents and a differential pair of detection currents derived from a differential pair of node voltages associated with the functional circuit. The counter generates the digital count based on the differential pair of amplified signals. The differential pair of feedback currents is controlled such that the magnitude difference between the differential pair of detection currents and the differential pair of feedback currents is within a tolerance limit. A power associated with the functional circuit is calibrated and monitored based on the digital count.

Methods and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and/or different transmitter architectures. One example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit with at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit with at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

Methods and apparatus for filtering a signal using a current-mode filter circuit implementing source degeneration. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor comprising a drain coupled to the input node; a second transistor comprising a drain coupled to the output node and comprising a gate coupled to a gate of the first transistor; a capacitive element coupled between the drain of the first transistor and the power supply node; a first resistive element coupled between the drain and the gate of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

Methods and apparatus for filtering a signal using a current-mode filter circuit implementing source degeneration. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor comprising a drain coupled to the input node; a second transistor comprising a drain coupled to the output node and comprising a gate coupled to a gate of the first transistor; a capacitive element coupled between the drain of the first transistor and the power supply node; a first resistive element coupled between the drain and the gate of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

A peak current mode PCM controller comprising control logic arranged to produce a series of digital control values derived from a voltage sense signal, control logic arranged to produce a digital slope compensation value, a first digital to analogue converter DAC arranged to receive the series of digital control values and output a corresponding analogue control voltage, a second DAC arranged to receive the digital slope compensation value and output a corresponding analogue slope compensation voltage, an analogue differential integrator arranged to receive the analogue control voltage and the analogue slope compensation voltage, integrate the analogue slope compensation voltage, subtract the integrated slope compensation voltage from the analogue control voltage, and output the result of the subtraction as an analogue output voltage, a comparator arranged to compare the analogue output voltage to a voltage of an analogue current sense signal and produce an output signal when the analogue current sense signal voltage is equal to or exceeds the analogue output voltage, and control logic arranged to produce a drive signal in response to the output signal.

A communication system includes a digital data processor that produces a digital data sample and one or more control bits. A serialized transmit interface assembles the digital data sample and the control bit(s) into first and second data packets of a data frame, and sends the data frame over a signal line. A serialized receive interface receives the data frame and produces a reconstructed digital data sample and the control bit(s) from the first and second data packets. A control circuit coupled to the serialized receive interface produces a control signal from the control bit(s). The communication system may include a converter circuit, which produces an RF input signal by performing a digital-to-analog conversion of the reconstructed digital data sample, and by upconverting the resulting analog data sample signal to RF. A power amplifier amplifies the RF input signal and modifies operation of a sub-circuit based on the control signal.

A noise filtering circuit, a digital to analog converter and an electronic device are provided. The noise filtering circuit comprises a first amplifier configured to receive a bias voltage at a first input terminal, receive a bias output voltage at a second input terminal though a feedback path, and compensate for a difference between the bias voltage and the bias output voltage; a first transistor connected to an output of the first amplifier and having a gate to which an off-voltage is applied; a first capacitor connected to the first transistor; a second capacitor connected to the output of the first amplifier; a second transistor connected to the second capacitor and having a gate to which an off-voltage is applied, and a second amplifier having an input terminal connected to the first capacitor and a second input terminal connected to the second transistor.

A method includes providing, by a signal source circuit of a sensing circuit, a signal to a sensor via a conductor. When the sensor is exposed to a condition and is receiving the signal, an electrical characteristic of the sensor affects the signal. The signal includes at least one of: a direct current (DC) component and an oscillating component. When the sensing circuit is in a noisy environment, transient noise couples with the signal to produce a noisy signal. The method further includes comparing, by a transient circuit of the sensing circuit, the noisy signal with a representation of the noisy signal. When the noisy signal compares unfavorably with the representation of the noisy signal, supplying, by the transient circuit, a compensation signal to the conductor. A level of the compensation signal corresponds to a level at which the noisy signal compares unfavorably with the representation of the noisy signal.

In described examples, a digital-to-analog converter includes an output, multiple most significant bit (MSB) connector resistors each having a resistance R??R, multiple least significant bit (LSB) connector resistors each having a resistance R, and multiple binary arm resistors each having a resistance 2R. The MSB connector resistors are coupled in a series beginning with the output and ending with a first one of the LSB connector resistors, and the LSB connector resistors are coupled in a series beginning with the first LSB connector resistor. A terminal of one of the binary arm resistors is coupled to an ending of the LSB connector resistor series, and a terminal of each of different remaining ones of the binary arm resistors is coupled between a different pair of the MSB and/or LSB connector resistors.