A mobile docking station (MDS) includes a surface through which the MDS can electrically and communicatively couple to a handheld mobile device (HMD) while remaining physically unattached from the MDS. The MDS power circuitry configured to electrically couple the MDS and the HMD while a surface of the HMD physically contacts the surface of the MDS, wherein the electrical coupling enables transferring of power between the MDS and the HMD. The MDS also includes communications circuitry configured to communicatively couple the MDS and the HMD while the surface of the HMD physically contacts the surface of the MDS, wherein the communicative coupling enables unidirectional or bidirectional communications between the MDS and HMD.

The present disclosure relates to a signal generator with self-calibration including a main digital-to-analog converter (DAC), a calibration DAC, a summing buffer structure, a two-path filter structure, an analog-to-digital converter (ADC), and a control system. The main DAC provides a main DAC output signal with main DAC distortion. The main DAC output signal is calibrated by a calibration DAC output signal to correct at least a portion of the main DAC distortion. The calibration DAC output signal includes information about the main DAC distortion and is generated by a feedback loop including the summing buffer structure, the two-path filter structure, the filter buffer, the ADC, the control system, and the calibration DAC.

The present disclosure relates to a signal generator with self-calibration including a main digital-to-analog converter (DAC), a calibration DAC, a summing buffer structure, a two-path filter structure, an analog-to-digital converter (ADC), and a control system. The main DAC provides a main DAC output signal with main DAC distortion. The main DAC output signal is calibrated by a calibration DAC output signal to correct at least a portion of the main DAC distortion. The calibration DAC output signal includes information about the main DAC distortion and is generated by a feedback loop including the summing buffer structure, the two-path filter structure, the filter buffer, the ADC, the control system, and the calibration DAC.

The present disclosure includes circuits and methods that adjust and correct duty cycles of circuits. The circuits and methods receive a signal from a first circuit and forward the received signal to a second circuit that retrieves a first setting (X) that provides a measure of duty cycle of the received signal. The circuits and methods then invert the received signal, retrain the second circuit based upon the inverted received signal, and retrieve a second setting (Y) of the retrained second circuit. The second setting (Y) provides a measure of duty cycle of the inverted received signal. The circuits and methods then adjust the duty cycle of the received signal based upon the first and second settings (X, Y) and further retrain of the second circuit to provide an improved duty cycle in a direction closer to 50 percent.

A host unit is provided between a remote radio head and a radio unit. The host unit performs a conversion between a digital optical signal used by the remote radio head and an analog optical signal used by the radio unit. A frequency of the analog optical signal converted by the host unit may be an intermediate frequency. The radio unit performs a conversion between an analog optical signal used by the host unit and an analog radio signal used by a user terminal. A frequency of the analog radio signal may be included in a millimeter wave band or radio frequency band.

A time-interleaved digital-to-analog converter (DAC) uses M DAC cores to convert a digital input signal whose digital input words are spread to different DAC cores to produce a final analog outputs. The M DAC cores, operating in a time-interleaved fashion, can increase the sampling rate several times compared to the sampling rate of just one DAC. However, sequential time-interleaving DAC cores often exhibit undesirable spurs at the output. To spread those spurs to the noise floor, the time-interleaving DAC cores can be selected at a pseudo randomized manner or in a specific manner which can break up the sequential or periodic manner of selecting the DAC cores.

A time-interleaved digital-to-analog converter (DAC) uses M DAC cores to convert a digital input signal whose digital input words are spread to different DAC cores to produce a final analog outputs. The M DAC cores, operating in a time-interleaved fashion, can increase the sampling rate several times compared to the sampling rate of just one DAC. However, sequential time-interleaving DAC cores often exhibit undesirable spurs at the output. To spread those spurs to the noise floor, the time-interleaving DAC cores can be selected at a pseudo randomized manner or in a specific manner which can break up the sequential or periodic manner of selecting the DAC cores.

The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

A system includes a non-transitory memory, a processor in operable communication with the memory, a digital-to-analog converter (DAC) and a transmitter. The memory stores bit position information associated with a first data. The bit position information includes absolute position data and relative position data for each bit of a plurality of bits of the first data. The processor can receive a data stream including the first data, and compress the first data to generate a second data representing the first data. The second data has a data structure that is arranged based on: (1) the first data, and (2) the bit position information. The DAC can receive a digital representation of the second data from the processor and convert the digital representation of the second data into an analog representation of the second data. The transmitter can then transmit the analog representation of the second data.