Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.

Some embodiments include apparatus and methods using a first digital-to-time converter (DTC) circuit to receive an input clock signal and generate a first clock signal based on the input clock signal, a second DTC circuit to receive the input clock signal and generate a second clock signal based on the input clock signal, and an output circuit to receive the first and second clock signals to generate an output clock signal based on the first and second clock signals.

A system includes a non-transitory memory, a processor in operable communication with the memory, a digital-to-analog converter (DAC) and a transmitter. The memory stores bit position information associated with a first data. The bit position information includes absolute position data and relative position data for each bit of a plurality of bits of the first data. The processor can receive a data stream including the first data, and compress the first data to generate a second data representing the first data. The second data has a data structure that is arranged based on: (1) the first data, and (2) the bit position information. The DAC can receive a digital representation of the second data from the processor and convert the digital representation of the second data into an analog representation of the second data. The transmitter can then transmit the analog representation of the second data.

A system includes a non-transitory memory, a processor in operable communication with the memory, a digital-to-analog converter (DAC) and a transmitter. The memory stores bit position information associated with a first data. The bit position information includes absolute position data and relative position data for each bit of a plurality of bits of the first data. The processor can receive a data stream including the first data, and compress the first data to generate a second data representing the first data. The second data has a data structure that is arranged based on: (1) the first data, and (2) the bit position information. The DAC can receive a digital representation of the second data from the processor and convert the digital representation of the second data into an analog representation of the second data. The transmitter can then transmit the analog representation of the second data.

Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC.

Audio content in a single-bit audio stream can be reproduced at a transducer by mapping the single-bit audio stream to symbols in a multi-bit audio stream. Volume control may be implemented, in part, in the digital domain and, in part, in the analog domain. In the digital domain, when converting the single-bit audio stream to a plurality of symbols, the plurality of symbols is selected based, at least in part, on audio content of the single-bit audio stream and a desired volume level. In the analog domain, when converting an analog current signal output from a current-steering DAC processing the plurality of symbols to an analog voltage signal, an analog gain value may be selected based, at least in part, on the desired volume level.

Embodiments of the disclosure provide improved mismatch shaping for a digital to analog converter, the method including splitting an original input of a circuit into a plurality of time interleaved data streams; element rotation selection (ERS) logic to process the plurality of time interleaved data streams; and directing one of the plurality of time interleaved data streams to the ERS logic according to a decision of a data-weighted sigma-delta (SD) modulator. In other example implementations, the method can further include multiplexing one of the plurality of time interleaved data streams to be provided to a barrel shifter. In yet other examples, the method can include monitoring a difference between the plurality of time interleaved data streams as a basis for the directing such that a data sample rate for the digital to analog converter is reduced over a time interval.

A digital-to-analog converter includes an amplifier, a voltage relaxation circuit, a base current source, a first weighting current source, and at least one second weighting current source. The amplifier receives a reference voltage and a feedback voltage, and generates an output voltage according to the reference voltage and the feedback voltage. The base current source is coupled to an output end of the amplifier through the voltage relaxation circuit, and is configured to generate an adjustable base current. The first weighting current source generates an adjustable first weighting current between a reference ground end and one of a current load and the voltage relaxation circuit according to a first bit of input data. The second weighting current source generates at least one second weighting current according to at least one second bit of the input data.

A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.

A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.