Patent classifications
H03M1/66
RECEPTION DEVICE AND CLOCK GENERATING METHOD
An object of the present invention is to generate a clock also before reception of a packet in a reception device. A reception device has: a storage unit storing a true time-stamp included in a received packet including audio data and the true time-stamp expressing reproduction time of the audio data; a timer counting time; a dummy time-stamp generation unit generating a dummy time-stamp as a false time-stamp; a comparator comparing time based on the true time-stamp stored in the storage unit or the dummy time-stamp and time indicated by the timer; and a clock generation unit generating a clock in accordance with a comparison result of the comparator. The comparator performs comparison using the dummy time-stamp until a predetermined condition is satisfied and, after the predetermined condition is satisfied, performs comparison using the true time-stamp.
RECEPTION DEVICE AND CLOCK GENERATING METHOD
An object of the present invention is to generate a clock also before reception of a packet in a reception device. A reception device has: a storage unit storing a true time-stamp included in a received packet including audio data and the true time-stamp expressing reproduction time of the audio data; a timer counting time; a dummy time-stamp generation unit generating a dummy time-stamp as a false time-stamp; a comparator comparing time based on the true time-stamp stored in the storage unit or the dummy time-stamp and time indicated by the timer; and a clock generation unit generating a clock in accordance with a comparison result of the comparator. The comparator performs comparison using the dummy time-stamp until a predetermined condition is satisfied and, after the predetermined condition is satisfied, performs comparison using the true time-stamp.
CLOSED-LOOP DIGITAL COMPENSATION SCHEME
Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.
Multi-zone digital-to-analog converter (DAC)
A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M<K<L. The upsampling stage supplies analog output signal images in a plurality of Nyquist zones. In one aspect, the D/A stage supplies N deinterleaved analog values having a combined bandwidth of M Hz, where N(P/2)=M.
Amplifier with power dissipation reduction using single radio frequency digital-to-analog converter
The disclosed system and method provide for a CATV power amplifier in which power dissipation may be reduced by dynamically adjusting the amplifier bias such that the bias is high only when high peak output signals need to be produced. By combining a bias control signal and an RF data signal into a single signal produced by a single DA converter, the disclosed examples require fewer DA converters and a need to synchronize DA converters to produce each of the signals individually is eliminated. A low frequency signal may be added to the RF band to find an optimum compromise between positive and negative peak excursions produced by the amplifier such that an overall reduction in bias may be achieved.
Amplifier with power dissipation reduction using single radio frequency digital-to-analog converter
The disclosed system and method provide for a CATV power amplifier in which power dissipation may be reduced by dynamically adjusting the amplifier bias such that the bias is high only when high peak output signals need to be produced. By combining a bias control signal and an RF data signal into a single signal produced by a single DA converter, the disclosed examples require fewer DA converters and a need to synchronize DA converters to produce each of the signals individually is eliminated. A low frequency signal may be added to the RF band to find an optimum compromise between positive and negative peak excursions produced by the amplifier such that an overall reduction in bias may be achieved.
Universal input/output circuit
A universal input/output circuit for building automation is provided that may avoid issues related to capacitor soakage, thereby giving more accurate measurements of electric resistance. To mitigate capacitor soakage, the voltage between the input/output terminals is held constant. A programmable source drives a current through a resistor that connects to the input/output terminals. The circuit then measures a value of electrical resistance. The measurement yields a voltage signal which is transferred from the input of an analog-to-digital converter to the input of a digital-to-analog converter. A unity gain amplifier applies the output voltage of the digital-to-analog converter D/A to one of terminals. The circuit is configured such that the voltage signal at the output of the amplifier matches or substantially matches the voltage obtained from the resistance measurement.
Universal input/output circuit
A universal input/output circuit for building automation is provided that may avoid issues related to capacitor soakage, thereby giving more accurate measurements of electric resistance. To mitigate capacitor soakage, the voltage between the input/output terminals is held constant. A programmable source drives a current through a resistor that connects to the input/output terminals. The circuit then measures a value of electrical resistance. The measurement yields a voltage signal which is transferred from the input of an analog-to-digital converter to the input of a digital-to-analog converter. A unity gain amplifier applies the output voltage of the digital-to-analog converter D/A to one of terminals. The circuit is configured such that the voltage signal at the output of the amplifier matches or substantially matches the voltage obtained from the resistance measurement.
MULTI-ZONE DATA CONVERTERS
Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.
Low-Power and Compact Voltage Sensing Circuit
A voltage sensing circuit for a switching power converter includes a comparator having a comparator input stage that processes a voltage from a main DAC and a current from a tracking DAC.