A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

A multiple output, multiple impedance string digital-to-analog converter (DAC) circuit can provide a first output having a first resolution in response to a first digital input signal and a second output having a second resolution in response to a second digital input signal. A main impedance string and a secondary impedance string can be coupled using switching networks to provide a first DAC output. By coupling additional switches to the main impedance string and by sharing the main impedance string, a second DAC output can be realized.

A higher accuracy ADC circuit (e.g., in which the number of bits of the ADC circuit is twelve or greater) may need calibration multiple times during its working life to avoid bit weight errors. Described are techniques to address DAC element ratio errors between DAC element clusters in a DAC circuit in order to maintain the linear performance of analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits.

A higher accuracy ADC circuit (e.g., in which the number of bits of the ADC circuit is twelve or greater) may need calibration multiple times during its working life to avoid bit weight errors. Described are techniques to address DAC element ratio errors between DAC element clusters in a DAC circuit in order to maintain the linear performance of analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits.

Some embodiments include apparatus and methods using a first digital-to-time converter (DTC) circuit to receive an input clock signal and generate a first clock signal based on the input clock signal, a second DTC circuit to receive the input clock signal and generate a second clock signal based on the input clock signal, and an output circuit to receive the first and second clock signals to generate an output clock signal based on the first and second clock signals.

A method can include storing operation data in entries of memory mapped storage circuits of an integrated circuit (IC) device. The operation data of a single entry can include configuration data, an action value, and channel data having channel bits corresponding to different signal channels. Operation of the analog circuit can be configured with the configuration data. Signal channels to an analog circuit can be configured with channel data. In response to a first action value of the entry, selecting a next entry and the analog circuit and signal channels with configuration data of the next entry. In response to a second action value, ending operations of the analog circuit. Corresponding devices and systems are also disclosed.

A method can include storing operation data in entries of memory mapped storage circuits of an integrated circuit (IC) device. The operation data of a single entry can include configuration data, an action value, and channel data having channel bits corresponding to different signal channels. Operation of the analog circuit can be configured with the configuration data. Signal channels to an analog circuit can be configured with channel data. In response to a first action value of the entry, selecting a next entry and the analog circuit and signal channels with configuration data of the next entry. In response to a second action value, ending operations of the analog circuit. Corresponding devices and systems are also disclosed.

Systems, methods, and devices enhance management of components used in data converters. Methods include receiving an input at a data converter comprising a digital to analog converter (DAC), the digital to analog converter comprising a plurality of sensing elements, and performing, using the DAC, a first conversion operation based on the input and a first set of the plurality of sensing elements identified by a first pointer value. Methods also include determining a pointer increment value based, at least in part, on an output of the first conversion operation and a hysteresis threshold value, the pointer increment value being used to determine an amount by which the first pointer value is incremented, the hysteresis threshold value identifying a threshold for determination of the pointer increment value.

Some disclosed embodiments relate, generally, to shaping a waveform of a reference signal used by a driver of a touch sensor to limit electromagnetic emissions (EME) emitted by a touch sensor during a sensing operation. Some disclosed embodiments relate, generally, to a DAC referenced touch sensor driver and controlling an amount of EME emitted at a touch sensor using shapes of reference signals used by a touch detector to detect touches at the touch sensor. Some disclosed embodiments relate, generally, to compensating for effects of foreign noise at a touch sensor and, more specifically, to changing a shape of a reference signal based on a change to a sampling rate made to compensate for foreign noise.

A switched current source circuit, comprising first and second voltage source nodes; a load; a current source; and capacitor switching circuitry comprising a load node, a capacitor and a plurality of switches configured, based on a control signal, to adopt a biasing configuration followed by an active configuration, wherein in the biasing configuration, the load node is conductively connected to the second voltage source node to bias a voltage level at the load node, and the capacitor is connected so that it at least partly charges; and in the active configuration, the load node is conductively connected via the load to the first voltage source node, and via the capacitor to the current source to increase a potential difference between the first voltage source node and the load node.