A digital to analog converter (DAC) includes a first amplifier configured to receive a first bit of a data block as an input and output a first signal based on a value of the first bit of the data block, a first filter circuit configured to filter the first signal, an output configured to output an analog signal based on a combination of the filtered first signal and a second signal that represents a value of a second bit of the data block.

A digital to analog converter (DAC) includes a first amplifier configured to receive a first bit of a data block as an input and output a first signal based on a value of the first bit of the data block, a first filter circuit configured to filter the first signal, an output configured to output an analog signal based on a combination of the filtered first signal and a second signal that represents a value of a second bit of the data block.

Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.

A data driver includes a digital to analog converter, a buffer and a buffer controller. The digital to analog converter is configured to receive a data signal having a digital type and to convert the data signal into a data voltage having an analog type. The buffer is configured to buffer the data voltage and to output the data voltage. The buffer controller is configured to determine a parameter of the buffer based on previous line data of the data signal and present line data of the data signal.

An imaging system may include an image sensor. The image sensor may have an array of image pixels arranged in rows and columns. Each column of image pixels may be coupled to column readout circuitry via a corresponding column line. The column readout circuitry may include analog-to-digital conversion circuitry. The analog-to-digital conversion circuitry may include split MSB and LSB capacitor banks. The MSB capacitor bank may include capacitors selectively coupled to a coarse reference voltage or a fine reference voltage. The LSB capacitor bank may include capacitors electively coupled to the coarse reference voltage.

An imaging system may include an image sensor. The image sensor may have an array of image pixels arranged in rows and columns. Each column of image pixels may be coupled to column readout circuitry via a corresponding column line. The column readout circuitry may include analog-to-digital conversion circuitry. The analog-to-digital conversion circuitry may include split MSB and LSB capacitor banks. The MSB capacitor bank may include capacitors selectively coupled to a coarse reference voltage or a fine reference voltage. The LSB capacitor bank may include capacitors electively coupled to the coarse reference voltage.

A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.

The present invention relates to a new type of current driving circuit, which has high linearity during low current driving, comprising: a voltage-current conversion unit for converting an input voltage into a current; a digital analog converter (DAC) connected to an output terminal of the voltage-current conversion unit and for generating and outputting a voltage corresponding to an applied digital code; a field effect transistor having a first electrode connected to a load and a second electrode connected to a node connected to a resistor, and for allowing a current to flow to the load in response to a voltage applied to a gate; an amplifier for receiving the voltage output from the digital analog converter and a voltage generated by the resistor, generating a voltage for controlling such that a current flows from the field effect transistor, and applying same to the gate; a current supply source for supplying to the first electrode a current required for operating the field effect transistor in a saturation region; and a control unit for controlling the field effect transistor to operate in the saturation region, by activating the current supply source, if the field effect transistor operates in a region lower than a threshold voltage.

The present invention relates to a new type of current driving circuit, which has high linearity during low current driving, comprising: a voltage-current conversion unit for converting an input voltage into a current; a digital analog converter (DAC) connected to an output terminal of the voltage-current conversion unit and for generating and outputting a voltage corresponding to an applied digital code; a field effect transistor having a first electrode connected to a load and a second electrode connected to a node connected to a resistor, and for allowing a current to flow to the load in response to a voltage applied to a gate; an amplifier for receiving the voltage output from the digital analog converter and a voltage generated by the resistor, generating a voltage for controlling such that a current flows from the field effect transistor, and applying same to the gate; a current supply source for supplying to the first electrode a current required for operating the field effect transistor in a saturation region; and a control unit for controlling the field effect transistor to operate in the saturation region, by activating the current supply source, if the field effect transistor operates in a region lower than a threshold voltage.

A test and measurement instrument for analyzing signals using machine learning. The test and measurement instrument can determine a recovered clock signal based on the digital signal, set window positions for a fast Fourier transform of the digital signal, window the digital signal into a series of windowed waveform data based on the window positions, transform each of the windowed waveform data into a frequency-domain windowed waveform data using a fast Fourier transform, and determine high-order spectrum data of each of the frequency-domain windowed waveform data. The test and measurement instrument includes a neural network configured to receive the high-order spectrum data of the frequency-domain windowed transform data and classify each windowed waveform data based on the high-order spectrum data.