A test and measurement instrument for analyzing signals using machine learning. The test and measurement instrument can determine a recovered clock signal based on the digital signal, set window positions for a fast Fourier transform of the digital signal, window the digital signal into a series of windowed waveform data based on the window positions, transform each of the windowed waveform data into a frequency-domain windowed waveform data using a fast Fourier transform, and determine high-order spectrum data of each of the frequency-domain windowed waveform data. The test and measurement instrument includes a neural network configured to receive the high-order spectrum data of the frequency-domain windowed transform data and classify each windowed waveform data based on the high-order spectrum data.

A bandgap voltage reference circuit includes first and second transistors (e.g., 3-terminal BJTs or diode-connected BJTs), and a PTAT element (e.g., resistance or capacitance). The first transistor is at a first die location, and operates with a first base-emitter voltage. The second transistor is at a second die location, and operates with a second base-emitter voltage. Each of the first and second transistors may include multiple individual parallel-connected transistors. The PTAT element is operatively coupled to the first and second transistors such that a voltage difference between the first and second base-emitter voltages drops across the PTAT element. The first and second locations are separated by a distance (e.g., 1.5% or more of die length, or such that the respective centroids of the first and second transistor are spaced from one another). Such spatial distribution helps mitigate voltage shift induced by mechanical stress, and is insensitive to process variation.

A current output module includes a current output section configured to output a current, an AD conversion circuit configured to convert a detection voltage, which is a voltage according to the current output from the current output section, into a digital value, a controller configured to control a current output from the current output section on the basis of the digital value of the detection voltage output from the AD conversion circuit, and a reference voltage generator configured to generate a plurality of reference voltages. The controller includes a processor configured to cause the AD conversion circuit to convert each of the plurality of reference voltages into a digital value, and a corrector configured to calibrate the AD conversion circuit on the basis of each digital value obtained by conversion of the plurality of reference voltages.

A communication system includes a first system input adapted to be coupled to a DC transient current transitioning between a starting level and a target level on a pseudo-sinusoidal path and incudes a second system input adapted to be coupled to a HART signal. The system includes an adder circuit having an output, a first adder input coupled to the first system input and a second adder input coupled to the second system input. The adder circuit provides a superimposed signal comprising the HART signal and the DC transient current.

A communication system includes a first system input adapted to be coupled to a DC transient current transitioning between a starting level and a target level on a pseudo-sinusoidal path and incudes a second system input adapted to be coupled to a HART signal. The system includes an adder circuit having an output, a first adder input coupled to the first system input and a second adder input coupled to the second system input. The adder circuit provides a superimposed signal comprising the HART signal and the DC transient current.

Systems and methods for facilitating intercom communication for one or more quick-service restaurant drive-throughs are disclosed. Exemplary implementations may: capture sound from a customer placing an order; generate order information signals that represent the captured sound; encode signals to form order data packets; transmit the order data packets to a base station through a single pair of wires that is also used to provide power; decode information from the order data packets; and generate order sound based on the decoded information, such that the generated order sound is audible to a staff member of the quick service restaurant through a headset.

Systems and methods for facilitating intercom communication for one or more quick-service restaurant drive-throughs are disclosed. Exemplary implementations may: capture sound from a customer placing an order; generate order information signals that represent the captured sound; encode signals to form order data packets; transmit the order data packets to a base station through a single pair of wires that is also used to provide power; decode information from the order data packets; and generate order sound based on the decoded information, such that the generated order sound is audible to a staff member of the quick service restaurant through a headset.

An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.