The present invention provides a device for processing digital signals. The device comprises a digital signal source and a converter circuit having a current supply. The digital signal source outputs a codeword. The converter circuit receives the codeword from the digital signal source, receives a current at the current supply, and generates an output signal based on the codeword. The device generates the current based on the codeword.

The present invention provides a device for processing digital signals. The device comprises a digital signal source and a converter circuit having a current supply. The digital signal source outputs a codeword. The converter circuit receives the codeword from the digital signal source, receives a current at the current supply, and generates an output signal based on the codeword. The device generates the current based on the codeword.

An interface circuit, comprising: a signal line having signal, auxiliary and connection nodes defined therealong, the connection node for connection to a transmission line; signal-handling circuitry connected to the signal line at the signal node; an auxiliary circuit connected to the signal line at the auxiliary node; a signal pair of inductors connected in series along the signal line adjacent to and either side of the signal node; and an auxiliary pair of inductors connected in series along the signal line adjacent to and either side of the auxiliary node, wherein: the signal pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kS; the auxillary pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kA; and kS has a positive value and kA has a negative value.

A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form. The ADC comprises or is operably coupled to, a calibration circuit (650, 840) coupled to an input and an output of the at least one pair of comparator latches (336, 356) and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches (336, 356) in a time-Interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.

A digital-to-analog converter (“DAC”) converts digital image data into analog image signals. The DAC includes a stage outputting different voltages to a first output terminal and a second output terminal based on a voltage supplied to a first input terminal, a voltage supplied to a second input terminal, and a first input bit. The stage includes a switch circuit including switches that are alternately turned on by a control signal, and outputting an intermediate output voltage to a third output terminal based on a first input voltage supplied to the first input terminal and a second input voltage supplied to the second input terminal, and a selector outputting one of the first input voltage and the second input voltage, and the intermediate output voltage.

Apparatus and associated methods relate to generating a programmable differential threshold with a common mode signal derived from a received signal, and comparing a differential component of the received signal to the programmable differential threshold signal to improve signal loss detection accuracy in the presence of noise. In an illustrative example, the comparison may be performed in a signal loss detection circuit. The signal loss detection circuit may, for example, process a received input signal in an independent path in parallel with a main signal path. The programmable differential threshold may be set to a predetermined level as a function of an acceptable noise level. Based on the comparison, some implementations may advantageously respond to received signal loss, which may result from, for example, a signal path interruption.

Method and apparatus for sharing an analog signal for use by a plurality of devices are disclosed. In some implementations, the analog signal may be generated by a controller. The controller also may generate a control signal to determine when other devices use the analog signal. In one implementation, the control signal may be a token that may be transmitted and received by the other devices. If a device possess the token, then the device may use the analog signal. If the device does not possess the token, then the device may not use the analog signal. In another implementation, the controller may transmit a peer-to-peer message to a selected device. When the selected device receives the peer-to-peer message, then the selected device may use the analog signal. In this manner, the controller ensures that only one device at a time may use the analog signal.

A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.

A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.

The present disclosure relates to an integrated circuit with at least a first channel and a second channel. Each channel includes at least a DAC. The integrated circuit also includes a number of circuit elements interconnected between the channels. The circuit elements can be changed between a short circuit state and an open circuit state. Normally, each channel will operate independently of one another, using only the circuit components in its respective channel. However, the circuit elements are arranged to allow a user to combine part of the second channel with the first channel to improve the functionality and performance of the first channel. In particular, a state of the circuit elements can be chosen to combine components of the second channel with the first channel. For example, components (e.g. a sub-stage) of the second channel can be connected in parallel with corresponding components (e.g. a corresponding sub-stage) of the first channel. This may reduce the number of available channels, since the second channel can no longer be used as an independent channel. However, the performance of the first channel is enhanced. The presence of the circuit elements allow an end user to decide whether to sacrifice channel count for performance enhancements. For example, the user can provide user input to the integrated circuit to select how the channels are interconnected. Moreover, the integrated circuit does not use additional redundant circuitry to improve the first channel, and rather takes components from the second channel. As such, the integrated circuit can have a reduced size.