A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.

A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.

An exponential scale pulse width modulation (PWM) controller comprises a waveform generator circuit configured to generate a logarithmic waveform signal that has the shape of an increasing logarithm function; and a first comparator circuit including a first input to receive the logarithmic waveform signal, a second input to receive an input signal, and an output that provides a PWM control signal that includes signal pulses having a duty cycle that changes exponentially with respect to the input signal.

A security device includes a physical unclonable function (PUF) cell array including PUF cells connected with word lines and bit lines; first decoder circuitry connecting a first bit line connected to a target PUF cell with a first data line and a second bit line connected with a reference PUF cell to a second data line; a digital-to-analog converter (DAC) control circuit outputting first and second digital codes; a first DAC between a power supply voltage and the first data line, the first DAC generating a first analog output in response to the first digital code; a second DAC between the power supply voltage and the second data line, the second DAC generating a second analog output in response to the second digital code; and a sense amplifier comparing the first analog output and the second analog output and outputting a comparison result.

An open-loop digital-to-analog converter (DAC) circuit may include a delta-sigma modulator, a decode block responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, an analog output driver responsive to the plurality of DAC elements, a test signal generator configured to generate a test signal that is responsive to inputs of the plurality of DAC elements, and a synchronizer configured to enable replication of the test signal at an external test system coupled to the open-loop DAC circuit in order to generate a matching test signal at the external test system that matches the test signal generated by the test signal generator.

Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided a for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other I-DACs. Techniques are disclosed for decreasing mismatch among multiple I-DACs while improving efficiency of rotational dynamic element matching.

An optical phased array comprising a row-column driving mechanism is disclosed that reduces the number of digital to analog converter (DAC) channels to the number of rows N and the total number of interface pin counts down to the number of columns plus the number of rows M+N. Disclosed herein are systems and architecture for thermal waveguide-based phase shifters which improve thermal efficiency by having multi-pass waveguides arranged proximate a heating element in a serpentine fashion, which enables an increase in phase shift without increasing the length or the power consumption of the heating element by increasing the total length of waveguide being heated by a singular heating element.

An optical phased array comprising a row-column driving mechanism is disclosed that reduces the number of digital to analog converter (DAC) channels to the number of rows N and the total number of interface pin counts down to the number of columns plus the number of rows M+N. Disclosed herein are systems and architecture for thermal waveguide-based phase shifters which improve thermal efficiency by having multi-pass waveguides arranged proximate a heating element in a serpentine fashion, which enables an increase in phase shift without increasing the length or the power consumption of the heating element by increasing the total length of waveguide being heated by a singular heating element.

A sensor signal processing circuit including a delta-sigma analog-to-digital converter (ADC) and a control circuit is disclosed. The circuit is configured to adaptively activate one or more segments of current elements for sequential sampling periods based on a digital signal input to a DAC, wherein less than N current elements are allocated to each segment, each current element in an active segment is enabled and either contributes to a feedback signal of the DAC or does not contribute to the feedback signal, and current elements not in an active segment are disabled. The circuit can be integrated with an acoustic or other sensor as part of a sensor assembly.

A data driver includes a digital to analog converter, a buffer and a buffer controller. The digital to analog converter is configured to receive a data signal having a digital type and to convert the data signal into a data voltage having an analog type. The buffer is configured to buffer the data voltage and to output the data voltage. The buffer controller is configured to determine a parameter of the buffer based on previous line data of the data signal and present line data of the data signal.