Systems and methods directed to a quantum processing apparatus are provided. The apparatus comprises M solid-state qubits, where M>1, and control electronics, which are connected to the solid-state qubits. The control electronics comprise one or more qubit readout circuits, where each of the qubit readout circuits is connected to at least one of the solid-state qubits and comprises a downsampling analog-to-digital converter (hereafter DSADC). Each DSADC is configured to downsample analog signals obtained from the at least one of the solid-state qubits. Such a DSADC operates in the n.sup.th Nyquist zone of the spectrum of the analog signals obtained, so as to down-convert such analog signals from the n.sup.th Nyquist zone to the m.sup.th Nyquist zone of the spectrum, where n>m≥1, prior to sampling the analog signals to convert them into digital signals, in operation. One or more embodiments of the invention are further directed to a related method of operating such a quantum processing apparatus.

Techniques and circuitry for wavelength monitor and control are disclosed herein. The disclosed wavelength monitor and control circuitry and techniques are designed to realize a multi-channel DWDM optical link by using a photonic receiver that dynamically adjusts resonant wavelengths of the microring drop filter (MDF), as needed. The wavelength monitor and control circuitry can monitor and control the resonant wavelengths of multiple MDFs for a DWDM silicon photonics receiver with minimum power and area overhead. In an embodiment, circuitry for an optical receiver comprises an MDF having resonant wavelength for multiple DWDM channels, and circuitry to control and monitor the resonant wavelength of the MDF in real-time and in manner that compensates for deviation between actual resonant wavelength of the MDF and the incident optical wavelength of the MDF.

An analog-to-digital converting system and a method with offset correction mechanisms are provided. The method includes steps of: obtaining a direct current offset of an output voltage of a digital analog conversion unit in a system; obtaining first capacitance weights and second capacitance weights sequentially from small to large; subtracting the direct current offset from a digital signal; and multiplying bit values of the digital signal respectively by the corresponding first capacitance weight value or second capacitance weight value to output a decode signal.

Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches and/or errors. The mismatches and/or errors can degrade the quality of the analog output. To extract the mismatches and/or errors, a transparent dither can be used. The mismatches and/or errors can be extracted by observing the analog output, and performing a cross-correlation of the observed output with a switching bit stream of the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the respective mismatches and/or errors.

The present general inventive concept is directed to a signal generation system, device, and method for meter testing, including a digital signal generator to generate an arbitrary digital test signal, a digital-to-analog converter to convert the arbitrary digital test signal to an analog test signal, a signal converter to convert the analog test signal to a differential pair of signals corresponding to the analog test signal, and a power signal generator including: an input module to receive the differential pair of signals; an amplifier to amplify the differential pair of test signals; and an output module to output an output differential pair of signals to a load, to feed back a proportional representation of the output differential pair of signals to the input module, and to receive the amplified differential pair of signals from the amplifier.

A system includes a multiplying digital-to-analog converter (MDAC). The system also includes an input-side component coupled to the MDAC and configured to provide a code to the MDAC. The system also includes a reference voltage source coupled to the MDAC and configured to provide a reference voltage to the MDAC. The MDAC comprises a nonlinear calibration circuit configured to adjust an output of the MDAC nonlinearly based on the code, the reference voltage, and an output of the nonlinear calibration circuit.

A digital-to-analog conversion device and a digital-to-analog conversion system with multiple digital-to-analog conversion cores is provided. At least some of the multiple digital-to-analog conversion cores may be operated with different clock signals, especially with clock signals of different clock frequencies. For this purpose, each digital-to-analog conversion stage is provided with multiple different clock signals and each stage individually selects one of the multiple clock signals.

Technologies relating to implementing two-stage ramp ADCs in crossbar array circuits for high performance matrix multiplication are disclosed. An example two-stage ramp ADC includes: a transimpedance amplifier configured to convert an input signal from current to voltage; a comparator connected to the transimpedance amplifier; a switch bias set connected to the comparator; a switch side capacitor in parallel with the switch bias set; a ramp side capacitor in parallel with the switch bias set; a ramp generator connected to the comparator via the ramp side capacitor, wherein the ramp generator is configured to generate a ramp signal; a counter; and a memory connected to the comparator, wherein the memory is configured to store an output of the comparator.

Technologies relating to implementing two-stage ramp ADCs in crossbar array circuits for high performance matrix multiplication are disclosed. An example two-stage ramp ADC includes: a transimpedance amplifier configured to convert an input signal from current to voltage; a comparator connected to the transimpedance amplifier; a switch bias set connected to the comparator; a switch side capacitor in parallel with the switch bias set; a ramp side capacitor in parallel with the switch bias set; a ramp generator connected to the comparator via the ramp side capacitor, wherein the ramp generator is configured to generate a ramp signal; a counter; and a memory connected to the comparator, wherein the memory is configured to store an output of the comparator.

A method and a system of calibrating a DC offset voltage on a resistor load are provided. The system may include a first operational amplifier, a second operational amplifier, a comparator, a digital signal processor, and a digital to analog convertor. At a calibration mode, under control of the digital signal processor, the system may utilize open-loop high gain characteristics of the first operational amplifier and the comparator to automatically detect and calibrate the DC offset voltage. At an operation mode, the system may automatically compensate the DC offset voltage based on the calibration of the DC offset voltage. In this way, the system and the method can automatically detect, calibrate, and compensate the DC offset voltage with reduced cost and technical complexity.