An electrical circuit includes a signal processing chain and a controller. The signal processing chain includes an integrator configured to integrate an input signal over an integration time. The controller is connected to a signal output of the signal processing chain to receive and evaluate an output signal of the signal processing chain. The controller is further configured to adapt the integration time based on the output signal.

A filter circuit includes: a division unit that divides an input signal and adds, to a tail end of a division block, of head data of the next division block, to generate an input block; a plurality of signal processing units that perform filtering of a feedback type on input blocks to generate output samples, and generate and output blocks; and a coupling unit that couples the output blocks. The signal processing unit outputs first output samples generated until a switching timing, and outputs second output samples generated by the signal processing unit after the timing. The switching timing is a timing within a period corresponding to the duplicated data, at which timing a difference between a first signal generated by the signal processing unit and a second signal generated by the signal processing unit is less than or equal to a threshold consecutively for a second data length.

A novel and useful digitally intensive event-driven quasi-level crossing (quasi-LC) delta modulator analog to digital converter (ADC) with adaptive resolution (AR) for Internet of Things (IoT) wireless networks. Minimizing the average sampling rate for sparse input signals significantly reduces the power consumed in data transmission, processing, and storage. The AR quasi-LC delta modulator quantizes the residue voltage signal with a 4-bit asynchronous successive approximation register (SAR) sub-ADC, which enables a straightforward implementation of LC and AR algorithms in the digital domain. The modulator achieves data compression by means of a globally signal dependent average sampling rate and achieves AR through a digital multilevel comparison window that overcomes the tradeoff between the dynamic range and the input bandwidth in conventional LC ADCs. Engaging the AR algorithm reduces the average sampling rate by a factor of three at the edge of the modulator's signal bandwidth.

A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (V.sub.in) and a plurality of converter circuits (105.sub.1-105.sub.N). Each converter circuit (105.sub.j) comprises a comparator circuit (70.sub.j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70.sub.j). Furthermore, each converter circuit (105.sub.j) comprises a one-bit current-output DAC (110.sub.j) having an input directly controlled from the output of the comparator circuit (70.sub.j) and an output connected to the second input of the comparator circuit (70.sub.j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits

A filter circuit includes: a division unit that divides an input signal and adds, to a tail end of a division block, of head data of the next division block, to generate an input block; a plurality of signal processing units that perform filtering of a feedback type on input blocks to generate output samples, and generate and output blocks; and a coupling unit that couples the output blocks. The signal processing unit outputs first output samples generated until a switching timing, and outputs second output samples generated by the signal processing unit after the timing. The switching timing is a timing within a period corresponding to the duplicated data, at which timing a difference between a first signal generated by the signal processing unit and a second signal generated by the signal processing unit is less than or equal to a threshold consecutively for a second data length.

An analog-to-digital converting apparatus includes a first stage converter which performs a first analog-to-digital conversion on an input analog signal during a first stage period, a second stage converter which receives a first residue from the first stage converter amplified by a first gain and which performs a second analog-to-digital conversion during a second stage period, and a recombination logic circuit which combines a first output signal from the first stage converter and a second output signal from the second stage converter into an output digital signal that corresponds to the input analog signal. The second stage converter generates a second stage feedback signal obtained by amplifying the second output signal by the first gain during a first sub-cycle in the second stage period, and generates a second output signal of a second sub-cycle subsequent to the first sub-cycle based on the second stage feedback signal.

A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

A system includes an analog-to-digital converter configured to convert an analog signal generated by a digital sensor into a digital signal, and a testing apparatus configured to be enabled after the analog-to-digital converter operates in a testing mode, wherein the testing apparatus comprises a filter configured to receive the digital signal from the analog-to-digital converter, and apply a filtering process to the digital signal, a control circuit configured to terminate the filtering process after an output of the control circuit reaches a predetermined reference value, and a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process.