The present disclosure relates to a compression/encoding apparatus and method, a decoding apparatus and method, and a program that allow for provision of a lossless compression technology with higher compression ratio.

A GOB data configuration section configures GOB data with a group of digital data that includes a plurality of blocks by treating a frame of delta-sigma-modulated digital data as a block. A table generation section generates a conversion table for encoding the GOB data. An encoding section compresses and encodes the digital data of each block included in the GOB data by using the conversion table. The present technology is applicable, for example, to audio signal compression and encoding, and so on.

The present disclosure relates to a compression/encoding apparatus and method, a decoding apparatus and method, and a program that allow for provision of a lossless compression technology with higher compression ratio.

A GOB data configuration section configures GOB data with a group of digital data that includes a plurality of blocks by treating a frame of delta-sigma-modulated digital data as a block. A table generation section generates a conversion table for encoding the GOB data. An encoding section compresses and encodes the digital data of each block included in the GOB data by using the conversion table. The present technology is applicable, for example, to audio signal compression and encoding, and so on.

Provided is a transmission system including: a signal processing apparatus 2 configured to transmit, via a signal cable 4, a delta-sigma modulated signal obtained by performing delta-sigma modulation on a transmission signal that is an RF signal; and a wireless apparatus 3 configured to transmit, via the signal cable 4, a reception signal that is an RF signal. The signal processing apparatus 2 transmits the delta-sigma modulated signal to the wireless apparatus 3, and the wireless apparatus 3 transmits the reception signal to the signal processing apparatus 2. In the delta-sigma modulated signal, quantization noise is suppressed at the frequency of the reception signal. The reception signal is transmitted to the signal processing apparatus 2 while the delta-sigma modulated signal is being transmitted to the wireless apparatus 3.

Techniques to compensate non-radiation hardened components for changes in performance that result from exposure to radiation. The techniques of this disclosure apply a predetermined bias signal to a representative non-radiation hardened component while a system is in use. The system determines whether there is a performance change in characteristics, such as voltage response, frequency response, gain, or other characteristics. The system may determine a compensation factor that may restore the desired signal output from the component. The system may compensate a second identical component that is in use in the system with the compensation factor. The component receiving the predetermined bias signal acts as a characterization dosimeter of the component in use in the system. A number of radiation vulnerable components may be characterized simultaneously with exact representative parts. The system may compensate identical component in use in the system with the appropriate compensation factor for each.

A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.

A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.

A failure determination circuit includes a first A/D conversion circuit that continuously A/D converts a first analog signal based on a first physical quantity measurement signal, a switching circuit that receives a plurality of signals including a second analog signal based on the first physical quantity measurement signal and a first reference voltage and outputs the plurality of signals in a time division manner, a second A/D conversion circuit that A/D converts the output of the switching circuit, and a determination circuit, and the determination circuit determines a failure of the first A/D conversion circuit using a signal based on a first digital signal obtained by A/D converting the first analog signal by the first A/D conversion circuit and a signal based on a second digital signal obtained by A/D converting the second analog signal by the second A/D conversion circuit.

A failure determination circuit includes a first A/D conversion circuit that continuously A/D converts a first analog signal based on a first physical quantity measurement signal, a switching circuit that receives a plurality of signals including a second analog signal based on the first physical quantity measurement signal and a first reference voltage and outputs the plurality of signals in a time division manner, a second A/D conversion circuit that A/D converts the output of the switching circuit, and a determination circuit, and the determination circuit determines a failure of the first A/D conversion circuit using a signal based on a first digital signal obtained by A/D converting the first analog signal by the first A/D conversion circuit and a signal based on a second digital signal obtained by A/D converting the second analog signal by the second A/D conversion circuit.

An A/D converter includes: an integrator circuit executing modulation to an analog signal to be converted; an adder outputting an addition result of at least an output signal of the integrator circuit and a first reference signal as a reference signal of modulation; a quantizer receives an output signal of the integrator circuit, an output signal of the adder, and a second reference signal as a reference signal in cyclic A/D conversion to generate a result of quantization of the output signal of the integrator circuit and the output signal of the adder; and a controller is configured to switch between a modulation mode and a cyclic mode.

Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.