A continuous-time sigma delta modulator circuit includes a scaling circuit that scales an input analog signal by a selectable range of different scaling factors in order to change a range of signal levels of the input analog signal to a desired range of signal levels in a scaled analog signal prior to conversion of the scaled analog signal to a digital signal. The scaling factor is selected based on the range of signal levels of the input analog signal in order to provide signal levels of the scaled signal within a desired range. The scaling circuit maintains current flow of the input analog signal at a substantially constant level regardless of the different scaling factors that are used to scale the input analog signal.

A signal processing apparatus includes: a difference signal acquirer configured to obtain a difference signal reflecting a change in an input signal at a preset time interval based on a reference signal; a signal amplifier configured to amplify the difference signal; and a signal restorer configured to generate an output signal by converting the amplified difference signal to a digital signal and summing the digital signal.

A signal processing apparatus includes: a difference signal acquirer configured to obtain a difference signal reflecting a change in an input signal at a preset time interval based on a reference signal; a signal amplifier configured to amplify the difference signal; and a signal restorer configured to generate an output signal by converting the amplified difference signal to a digital signal and summing the digital signal.

An A/D converter includes an adder that calculates a difference between an analog input signal and a predicted value, a quantizer that quantizes the difference output from the adder to convert the analog input signal to a digital signal, a prediction filter that generates a predicted value from the digital signal output from the quantizer, and a D/A converter that converts the predicted value from a digital signal to an analog signal and output the predicted value to the adder. The predicted value before being subjected to conversion to the analog signal by the D/A converter defines and functions as an A/D converted output of the analog input signal input to the adder.

An A/D converter includes an adder that calculates a difference between an analog input signal and a predicted value, a quantizer that quantizes the difference output from the adder to convert the analog input signal to a digital signal, a prediction filter that generates a predicted value from the digital signal output from the quantizer, and a D/A converter that converts the predicted value from a digital signal to an analog signal and output the predicted value to the adder. The predicted value before being subjected to conversion to the analog signal by the D/A converter defines and functions as an A/D converted output of the analog input signal input to the adder.

The present disclosure relates to a compressive encoding apparatus, a compressive encoding method, a decoding apparatus, a decoding method, and a program which can provide a lossless compression technology having a higher compression rate. An encoding unit of the compressive encoding apparatus converts M bits of a -modulated digital signal into N bits (M>N) with reference to a first conversion table, and when the M bits are not able to be converted into the N bits with the first conversion table, converts the M bits into the N bits with reference to a second conversion table. When the number of bit patterns of the N bits is P, the first conversion table is a table storing (P1) number of codes having higher generation frequencies for past bit patterns, and the second conversion table is a table storing (P1) number of codes having higher generation frequencies for past bit patterns, which follow those of the first conversion table. The present disclosure is applicable to a compressive encoding apparatus that compressively encoding an audio signal, and the like, for example.

The present disclosure relates to a compressive encoding apparatus, a compressive encoding method, a decoding apparatus, a decoding method, and a program which can provide a lossless compression technology having a higher compression rate. An encoding unit of the compressive encoding apparatus converts M bits of a -modulated digital signal into N bits (M>N) with reference to a first conversion table, and when the M bits are not able to be converted into the N bits with the first conversion table, converts the M bits into the N bits with reference to a second conversion table. When the number of bit patterns of the N bits is P, the first conversion table is a table storing (P1) number of codes having higher generation frequencies for past bit patterns, and the second conversion table is a table storing (P1) number of codes having higher generation frequencies for past bit patterns, which follow those of the first conversion table. The present disclosure is applicable to a compressive encoding apparatus that compressively encoding an audio signal, and the like, for example.

A band-pass filter is described comprising a first first-order filter stage comprising a first resistor characterised by a first impedance and connected to a first node, referred to as a filter input node, and, through a second node to a first reactive component connected to a third node, the first impedance being such that a first current therethrough is dependent on the difference between the voltages at the first and second nodes; and a second first-order filter stage comprising a second resistor characterised by a second impedance and connected to the second node, and, through a fourth node, to a second reactive component connected to a fifth node. The second impedance is such that a second current therethrough is dependent on the negative of the sum of the voltages at the second and fourth nodes. The band-pass filter further comprises summing means for summing the voltages at the second and fourth nodes to output a voltage at a sixth node.

Aspects of the present disclosure include a frequency-to-current (F2I) circuit and systems, methods, devices, and other circuits related thereto. The F2I circuit is implemented with a delta-modulator-based control loop to settle and maintain an operating point on a bias node. The control loop provides an integral of an output of a comparator, and the comparator compares it to a self-built voltage reference. Upon powering on the circuit, an integrator in the control loop starts to integrate the charge on both a bias voltage and an internal voltage to provide a settling process for the internal voltage to approximate the reference voltage and for the bias voltage to approximate a predetermined operating point of the bias node. After the circuit has settled, the comparator's output charge toggles and the internal voltage and bias voltage become sawtooth-like waveforms at the reference voltage and operating points, respectively.

Aspects of the present disclosure include a frequency-to-current (F2I) circuit and systems, methods, devices, and other circuits related thereto. The F2I circuit is implemented with a delta-modulator-based control loop to settle and maintain an operating point on a bias node. The control loop provides an integral of an output of a comparator, and the comparator compares it to a self-built voltage reference. Upon powering on the circuit, an integrator in the control loop starts to integrate the charge on both a bias voltage and an internal voltage to provide a settling process for the internal voltage to approximate the reference voltage and for the bias voltage to approximate a predetermined operating point of the bias node. After the circuit has settled, the comparator's output charge toggles and the internal voltage and bias voltage become sawtooth-like waveforms at the reference voltage and operating points, respectively.