A delta-sigma modulator architecture with idle tone suppression based on injecting an out-of-band signal includes: modulator input circuitry to provide a modulator input signal; modulator loop circuitry to quantize the modulator input signal to generate a modulator output signal at an oversampling frequency, and to provide a feedback signal. Digital filtering circuitry filters the modulator output signal to provide a digital output signal at a data rate frequency related to the oversampling frequency by a defined oversampling ratio. Out-of-band (OoB) signal generator circuitry injects a deterministic OoB injection signal at a defined OoB frequency outside of a target frequency band. The modulator input circuitry combines the analog input signal, the feedback signal, and the OoB injection signal into the modulator input signal. The digital filtering circuitry filters the OoB injection signal. The OoB injection signal can be selectively defined to suppress idle tones generated in the modulator loop circuitry.

A digital microphone compresses a large voltage swing signal from a MEMS capacitor to a signal suitable for processing by integrated circuitry. The compression may be performed in an analog domain by selectively coupling adjustment capacitors in parallel to the MEMS capacitor. The digital microphone may decompress the signal in the digital domain using a decompression technique substantially an inverse of the compression performed in the analog domain.

Described herein is an improved apparatus for increasing the performance of a modulator, which may function as an ADC. In one embodiment, the modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.

A radio frequency (RF) transmitter includes a set of input ports to receive baseband, a set of filter banks for each input port that includes a plurality of digital polyphase interpolation filters, and a set of oscillators banks, wherein each oscillator bank includes a plurality of polyphase Digital Direct Synthesizer (DDS) corresponding to the plurality of digital polyphase interpolation filters. The RF transmitter includes a set of mixer banks to mix corresponding sequences of samples of digital waveform, a parallel digital combiner to combine in-phase sequences of interpolated baseband phased samples, and a pulse encoder to modulate and encode the plurality of sequences of multiband upconverted samples. The RF transmitter converts a plurality of encoded multi-band signals into a RF bitstream and an E/O interface to convert the RF bitstream.

Configuration information is generated for a configurable mixed-signal system. Analog requirements for operating the configurable mixed-signal system are gathered. A simulation model of a delta-sigma modulator is received. A simulation based on the simulation model of the delta-sigma modulator is performed to obtain parameter settings for the delta-sigma modulator. The obtained parameter settings are used to build at least a portion of a description of the configurable mixed-signal system. The description of the configurable mixed signal system is synchronized to receive configuration information.

The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter.

A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

Provided is a semiconductor device including: a first modulation circuit configured to receive a first sound source signal, sigma-delta modulate a signal based on the first sound source signal, and output a first sigma-delta modulated signal; a second modulation circuit configured to pulse-width modulate a signal based on the first sigma-delta modulated signal, and output a first pulse-width modulated signal; a first modulation inspection circuit configured to inspect the first modulation circuit; and a second modulation inspection circuit configured to inspect the second modulation circuit, in which the first modulation inspection circuit and the second modulation inspection circuit are separated from each other.

A radio frequency (RF) transmitter includes a set of input ports to receive baseband, a set of filter banks for each input port that includes a plurality of digital polyphase interpolation filters, and a set of oscillators banks, wherein each oscillator bank includes a plurality of polyphase Digital Direct Synthesizer (DDS) corresponding to the plurality of digital polyphase interpolation filters. The RF transmitter includes a set of mixer banks to mix corresponding sequences of samples of digital waveform, a parallel digital combiner to combine in-phase sequences of interpolated baseband phased samples, and a pulse encoder to modulate and encode the plurality of sequences of multiband upconverted samples. The RF transmitter converts a plurality of encoded multi-band signals into a RF bitstream and an E/O interface to convert the RF bitstream.

A capacitance measure circuit includes a charge to voltage converter (CVC), and the CVC includes an excitation signal generation circuit that is arranged to generate and connect an excitation signal to a first terminal of a capacitance sensor, a differential amplifier, a first switch circuit, and at least one first variable capacitor. The inverting input terminal of the differential amplifier is arranged to receive a sensing capacitance value from a second terminal of the capacitance sensor. The first switch circuit is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier, and is connected in parallel with the at least one first variable capacitor at the inverting input terminal and the non-inverting output terminal of the differential amplifier.