Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter.

Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

A differential output current digital-to-analog converter (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.

A physical quantity sensor module includes: a resonant frequency shift based physical quantity sensor whose frequency adjusts with a adjust in physical quantity; a reference signal oscillator which outputs a reference signal; a frequency delta-sigma modulator which performs frequency delta-sigma modulation of the reference signal, using an operation signal based on a measurement target signal as an output from the resonant frequency shift based physical quantity sensor, and generates a frequency delta-sigma modulated signal; a first low-pass filter provided on an output side of the frequency delta-sigma modulator and operating synchronously with the measurement target signal as the output from the resonant frequency shift based physical quantity sensor; and a second low-pass filter provided on an output side of the first low-pass filter and operating synchronously with the reference signal.

A method of processing an analog signal includes receiving, into signal processing circuitry from compensation circuitry, an offset compensation signal, the offset compensation signal having (i) a polarity opposite a polarity of a gain error of the signal processing circuitry and (ii) a magnitude equal to a nominal compensation value plus a deviation. The method includes generating, by the signal processing circuitry, an output signal based on an analog signal received into the signal processing circuitry, including applying the offset compensation signal to an intermediate signal generated by the signal processing circuitry. The method includes scaling the output signal based on the deviation between the magnitude of the offset compensation signal and the nominal compensation value.

Quantisation methods are provided which employ dither techniques to reduce the noise penalty in certain circumstances whilst still removing noise modulation. One method relates to reducing the wordwidth of audio by one bit, while another method relates to burying one bit of data in a pair of signal samples.

A clock generator comprise a delta-sigma modulation, DSM, for generating a division control signal and a phase control signal, an oscillator, for generating an oscillation signal with a first frequency, an adjustable frequency divider, for performing a division operation on the oscillation signal according to the division control signal, to generate a first division signal and a second division signal with a second frequency, and a phase interpolator, PI, for performing a phase interpolation operation on the first and second division signals according to the phase control signal, to generate an output signal with an output frequency, wherein the first frequency is greater than the second frequency.

A frequency delta sigma modulation signal output circuit includes a phase modulation circuit that outputs a phase modulation signal based on a delay signal obtained by delaying a signal to be measured, in synchronization with the signal to be measured, and a frequency ratio digital conversion circuit that generates a frequency delta sigma modulation signal using a reference signal and the phase modulation signal.

A physical quantity sensor module includes: a resonant frequency shift based physical quantity sensor whose frequency adjusts with a adjust in physical quantity; a reference signal oscillator which outputs a reference signal; a frequency delta-sigma modulator which performs frequency delta-sigma modulation of the reference signal, using an operation signal based on a measurement target signal as an output from the resonant frequency shift based physical quantity sensor, and generates a frequency delta-sigma modulated signal; a first low-pass filter provided on an output side of the frequency delta-sigma modulator and operating synchronously with the measurement target signal as the output from the resonant frequency shift based physical quantity sensor; and a second low-pass filter provided on an output side of the first low-pass filter and operating synchronously with the reference signal.