A system and method for providing error control coding for backhaul applications are disclosed. Data is first encoded using Reed-Solomon (RS) coding. The output RS blocks are then turbo coded. The size of the output RS blocks is selected to match the input of the turbo encoder. The bits from the RS blocks may be interleaved to create the input turbo blocks. Cyclic Redundancy Check (CRC) parity bits may be added to the data prior to RS coding.

There is provided a method for generating a burst error correction code. The method comprises: setting a mother code; defining a syndrome set corresponding to each burst error pattern for at least two burst error patterns to be corrected based on the mother code; shortening a column of a PCM (parity check matrix) of the mother code so that the defined syndrome sets are relatively prime; and designing an error correction code for the each burst error pattern based on an optimal generator polynomial maximizing a length of the shortened code within a range of a length of a parity bit of the mother code or a syndrome vector included in the syndrome set that is relatively prime.

A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.

There is provided an apparatus including an acquisition unit that acquires an information block generated from transmission data for a user and subjected to error correction coding, and an interleaving unit that interleaves a bit sequence of the information block using an interleaver unique to the user. The interleaving unit interleaves the bit sequence by interleaving each of two or more partial sequences obtained from the bit sequence.

The disclosed systems and methods for encoding, by a polar encoder, K message bits into an encoded message bits sequence C(M) using polar codes, where K and M are integer values and M is greater than or equal to K; rearranging, by an interleaver, the encoded message bits sequence C(M) to rearranged encoded message bits sequence C′(M) such that a C(i)th bit and a $C\left(\frac{M}{2}+i\right)$
th bit of the encoded message bits sequence C(M) are arranged together, where i is an integer value that varies between 1 to $\frac{M}{2};$
mapping, by a bits-to-symbol mapper, the rearranged encoded message bits sequence C(M) to N non-binary symbols, where N is an integer value; and processing, by a transmitter symbol processor, the N non-binary symbols to transmit the processed non-binary symbols towards a receiver.

The disclosed systems and methods for encoding, by a polar encoder, K message bits into an encoded message bits sequence C(M) using polar codes, where K and M are integer values and M is greater than or equal to K; rearranging, by an interleaver, the encoded message bits sequence C(M) to rearranged encoded message bits sequence C′(M) such that a C(i)th bit and a $C\left(\frac{M}{2}+i\right)$
th bit of the encoded message bits sequence C(M) are arranged together, where i is an integer value that varies between 1 to $\frac{M}{2};$
mapping, by a bits-to-symbol mapper, the rearranged encoded message bits sequence C(M) to N non-binary symbols, where N is an integer value; and processing, by a transmitter symbol processor, the N non-binary symbols to transmit the processed non-binary symbols towards a receiver.

A parity interleaving apparatus and method for fixed length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

The present disclosure provides techniques for bandwidth constrained communication systems with frequency domain information processing. A bandwidth constrained equalized transport (BCET) communication system can include a transmitter, a communication channel, and a receiver. The transmitter can include a pulse-shaping filter that intentionally introduces memory into a signal in the form of inter-symbol interference, an error control code (ECC) encoder, a multidimensional fast Fourier transform (FFT) processing block that processes the signal in the frequency domain, and a first interleaver. The receiver can include an information-retrieving equalizer, a deinterleaver with an ECC decoder, and a second interleaver joined in an iterative ECC decoding loop. The communication system can be bandwidth constrained, and the signal can comprise an information rate that is higher than that of a communication system without intentional introduction of the memory at the transmitter.

A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.