Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a transmitter device may segment a plurality of bits of a communication into a first set of bits and a second set of bits; process the first set of bits using a first processing chain and the second set of bits using a second processing chain, wherein the first set of bits is mapped to most significant bits (MSBs) of one or more symbols of a composite constellation and the second set of bits is mapped to least significant bits (LSBs) of the one or more symbols of the composite constellation, and wherein the composite constellation is formed from a plurality of lower order constellations; modulate the first set of bits and the second set of bits to generate a set of modulated symbols; and transmit the set of modulated symbols. Numerous other aspects are provided.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a transmitter device may segment a plurality of bits of a communication into a first set of bits and a second set of bits; process the first set of bits using a first processing chain and the second set of bits using a second processing chain, wherein the first set of bits is mapped to most significant bits (MSBs) of one or more symbols of a composite constellation and the second set of bits is mapped to least significant bits (LSBs) of the one or more symbols of the composite constellation, and wherein the composite constellation is formed from a plurality of lower order constellations; modulate the first set of bits and the second set of bits to generate a set of modulated symbols; and transmit the set of modulated symbols. Numerous other aspects are provided.

Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

A method of encoding input data includes receiving the input data that includes a plurality of input words including a first input word and a second input word, generating a plurality of converted words including a first converted word and a second converted word, the first converted word being based at least on the first input word, the second converted word being based on the first converted word and the second input word, identifying a key value based on the plurality of converted words, and generating a plurality of coded words based on the key value and the plurality of converted words.

A low-complexity selective mapping method using cyclic redundancy check is provided. In performing coding, a transmitter adds a check bit to information bits to be transmitted to obtain modulated data. Demodulation is performed on an M-order modulation symbol received by a receiver to obtain a decoding result of a coding polynomial of the modulation symbol and bit information received by the receiver. A modulo-2 division result of the decoding result of the coding polynomial and a generation polynomial is calculated. In a case that a remainder of the modulo-2 division result is equal to zero, if the modulated data corresponding to the same index value of the receiver and the transmitter are identical, a current iteration is stopped, and a current value is outputted as a phase rotation sequence index recovery value. Finally, the receiver obtains a decoded signal.

Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose-Chaudhuri-Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose-Chaudhuri-Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.

Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose-Chaudhuri-Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose-Chaudhuri-Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.

Methods, systems, and devices for generating a balanced codeword protected by an error correction code are described. A memory device may receive data bits for storage. Based on the data bits, the memory device may generate a codeword that includes the data bits, parity bits, and placeholder bits. The memory device may balance the codeword by inverting one or more packets of the codeword. After balancing the codeword, the memory device may store at least a portion of the codeword in memory so that a later operation or a decoding process reveals the packets that were inverted as part of the balancing process. Accordingly, the memory device may re-invert the appropriate packets to recover the original data bits.

An error rate measuring apparatus includes: an operation unit that sets a codeword length, an FEC symbol length, and an FEC symbol error threshold; error counting unit for counting FEC symbol error and an uncorrectable codeword; a display unit that performs display by setting one zone of a display area as one FEC symbol length, matching a zone length of a horizontal axis of the display area with one codeword length, and performing line feed in codeword length units according to presence or absence of the FEC symbol error in FEC symbol length units based on a counting result; search unit for searching for the uncorrectable codeword starting from the cursor on the identification display; and display control unit for performing display control of the cursor at a position of a head error of the searched uncorrectable codeword.