H03M13/31

Method and apparatus for vertical layered decoding of quasi-cyclic low-density parity check codes using predictive magnitude maps

A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.

Method and apparatus for vertical layered decoding of quasi-cyclic low-density parity check codes using predictive magnitude maps

A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.

METHOD AND APPARATUS FOR SHORTENING AND PUNCTURING NON-BINARY CODE

The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present invention relates to a method and a device for efficiently shortening and puncturing a non-binary LDPC code, the method for a transmitter shortening and puncturing a non-binary code being capable of supporting various modulation methods by using a single non-binary code, and the method comprising the steps of: shortening, on the basis of a modulation method, at least one information bit in at least one information symbol constituting the non-binary code; encoding the at least one information symbol having a shortened information bit; and puncturing, on the basis of the modulation method, at least one parity code in at least one parity symbol obtained through the encoding step.

METHOD AND APPARATUS FOR SHORTENING AND PUNCTURING NON-BINARY CODE

The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present invention relates to a method and a device for efficiently shortening and puncturing a non-binary LDPC code, the method for a transmitter shortening and puncturing a non-binary code being capable of supporting various modulation methods by using a single non-binary code, and the method comprising the steps of: shortening, on the basis of a modulation method, at least one information bit in at least one information symbol constituting the non-binary code; encoding the at least one information symbol having a shortened information bit; and puncturing, on the basis of the modulation method, at least one parity code in at least one parity symbol obtained through the encoding step.

METHODS AND SYSTEMS FOR HIGH BANDWIDTH COMMUNICATIONS INTERFACE

Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between a transmitting device and a receiving device operating at high speed with low power utilization. Communication is performed using group signaling over sets of four wires using a vector signaling code, where each wire of a set carries a low-swing signal that may take on one of four signal values. Topologies and designs of wire sets are disclosed with preferred characteristics for group signaling communications.

Encoding circuit, decoding circuit, encoding method, decoding method, and transmitting device
11431354 · 2022-08-30 · ·

An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit stings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

Encoding circuit, decoding circuit, encoding method, decoding method, and transmitting device
11431354 · 2022-08-30 · ·

An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit stings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

SIGNAL ENCODING METHOD AND APPARATUS AND SIGNAL DECODING METHOD AND APPARATUS

A spectrum coding method includes quantizing spectral data of a current band based on a first quantization scheme, generating a lower bit of the current band using the spectral data and the quantized spectral data, quantizing a sequence of lower bits including the lower bit of the current band based on a second quantization scheme, and generating a bitstream based on a upper bit excluding N bits, where N is 1 or greater, from the quantized spectral data and the quantized sequence of lower bits.

SIGNAL ENCODING METHOD AND APPARATUS AND SIGNAL DECODING METHOD AND APPARATUS

A spectrum coding method includes quantizing spectral data of a current band based on a first quantization scheme, generating a lower bit of the current band using the spectral data and the quantized spectral data, quantizing a sequence of lower bits including the lower bit of the current band based on a second quantization scheme, and generating a bitstream based on a upper bit excluding N bits, where N is 1 or greater, from the quantized spectral data and the quantized sequence of lower bits.

Reed-solomon coding for 40GBASE-T ethernet
09774420 · 2017-09-26 · ·

A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and logic to aggregate the Ethernet block data bits in accordance with a 512/513B code. A forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits.