An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit strings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit strings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).

A wireless communication method and protocol for wireless RF transmission of data, e.g. audio data, with low latency. The method involves a fixed part (FP) serving as synchronization master, and one or more portable parts (PP) being synchronization slaves. The FP performs scanning between a set of supported channels within one limited frequency band, such as within an ISM band. Further, the FP performs collecting measures of RF interference level on at least a plurality of the supported channels in response to the scanning, preferably using own interference level measurement and by collecting RSSI data from the PP for the supported channels. In response to these measures of RF interference level, the FP executes a selection algorithm for selecting and re-selecting first and second different frequencies for respective first and second duplex RF bearers from the set of supported channels to select the channels with least RF interference. Finally, the FP transmits, in one frame of such as 1 ms to 3 ms length, the same data packet on both of said first and second duplex RF bearer frequencies to the PP. This provides a roboust and low latency wireless interface suitable for Human Interface Devices and audio devices, e.g. for gaining equipment.

Decoders are provided for memory systems. A decoder includes a seed generator that generates seeds based on a physical address corresponding to a read request from a host; a descrambling module that receives a sequence from a storage area among, multiple storage areas, corresponding to the physical address, and descrambles the sequence using the seeds to generate multiple descrambled sequences; and a selector that selects one of descrambled sequences based on syndrome weight values of the descrambled sequences.

A network interface devices receives a plurality of bits, and encodes the plurality of bits into a plurality of bit blocks that includes a first set of bit blocks and a second set of bit blocks. The network interface device transcodes the first set of bit blocks to generate a third set of bit blocks, and aggregates the second set of bit blocks and the third set of bit blocks into an aggregated set of bit blocks. A first error correction encoder encodes a first portion of the bits in the aggregated set of bit blocks to generate a first set of encoded bits. A second error correction encoder encodes a second portion of the bits in the aggregated set of bit blocks to generate a second set of encoded bits. The network interface modulates the first set of encoded bits and the second set of encoded bits.

A network interface devices receives a plurality of bits, and encodes the plurality of bits into a plurality of bit blocks that includes a first set of bit blocks and a second set of bit blocks. The network interface device transcodes the first set of bit blocks to generate a third set of bit blocks, and aggregates the second set of bit blocks and the third set of bit blocks into an aggregated set of bit blocks. A first error correction encoder encodes a first portion of the bits in the aggregated set of bit blocks to generate a first set of encoded bits. A second error correction encoder encodes a second portion of the bits in the aggregated set of bit blocks to generate a second set of encoded bits. The network interface modulates the first set of encoded bits and the second set of encoded bits.

A spectrum coding method includes quantizing spectral data of a current band based on a first quantization scheme, generating a lower bit of the current band using the spectral data and the quantized spectral data, quantizing a sequence of lower bits including the lower bit of the current band based on a second quantization scheme, and generating a bitstream based on a upper bit excluding N bits, where N is 1 or greater, from the quantized spectral data and the quantized sequence of lower bits.

A spectrum coding method includes quantizing spectral data of a current band based on a first quantization scheme, generating a lower bit of the current band using the spectral data and the quantized spectral data, quantizing a sequence of lower bits including the lower bit of the current band based on a second quantization scheme, and generating a bitstream based on a upper bit excluding N bits, where N is 1 or greater, from the quantized spectral data and the quantized sequence of lower bits.