A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.

Apparatuses, systems, and methods are presented for error correction based on physical characteristics for memory. A controller may be configured to read a set of encoded bits from a set of cells of a memory array. The controller may be configured to divide the encoded bits into reliability groups based on one or more persistent physical characteristics associated with cells of the set of cells. The controller may be configured to provide reliability estimates based on the reliability groups to a soft decision decoder for decoding the encoded bits.

A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

Provided is a coding control method in a passive optical network (PON). The method includes acquiring a codeword length N corresponding to a service to be coded; acquiring a matched coding mode corresponding to the codeword length N in a preset table describing a correspondence between codeword length ranges and coding modes; and coding data of the service by using the matched coding mode. Further provided are a coding control apparatus in a PON, a communication device and a storage medium.

A storage device includes a memory array and a memory controller. The memory controller generates read and write commands for the memory array. An error correction code engine for the storage device is operable to use a plurality of different codeword sizes, different code rates, or different ECC algorithms. Logic is included that applies a selected codeword size, code rate or ECC algorithm in dependence on the operating conditions of the memory array.

A method includes, determining, for a batch rebuild process regarding a first batch threshold number of encoded data slices of a set of encoded data slices that need rebuilding, a target storage unit of target storage units of a set of storage units of the storage network is unavailable, where a data segment of data is dispersed storage error encoded into the set of encoded data slices, the set of encoded data slices is stored in the set of storage units, and the first batch threshold number of encoded data slices is to be stored in the target storage units. When the target storage unit becomes available before a second batch rebuild threshold number of encoded data slices of the set of encoded data slices is met, the method includes executing the batch rebuild process for the first batch threshold number of encoded data slices.

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

A data transmission method and apparatus are disclosed. The method includes a first communication apparatus obtains information bit information of an ith sub-block, where the information bit information of the ith sub-block includes information bits of the ith sub-block and an information bit length of the ith sub-block, and i is a positive integer; obtains a matrix order M of the RM corresponding to the first communication apparatus in the ith sub-block, where M is a positive integer; then obtains, based on M, a first P matrix and a first b vector that are used to generate an RM; then generates, based on the first P matrix and the first b vector, the RM sequence corresponding to the ith sub-block; and finally, outputs the RM sequence corresponding to the ith sub-block.