A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to interleave the parity bits and group-wise interleave a plurality of parity bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern to perform parity permutation; a puncturer configured to puncture at least some of the group-wise interleaved parity bit groups; and an additional parity generator configured to select at least some of the punctured parity bit groups to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern.

Example apparatus and methods control whether and when hybrid rateless Reed Solomon (RS) error correcting codes (ECC) for a message are produced, stored, and distributed. The control may be based on a property (e.g., reliability, error state, speed) of a message recipient. Example apparatus and methods may also control whether and when fountain codes for the message are produced, stored, and distributed. Once again, the control may be based on a property of a message or ECC recipient. Both the hybrid rateless RS ECC and the fountain codes may be produced from data stored in a modified RS matrix. The modified RS matrix may store row-centric error detection codes (EDC) instead of conventional cyclic redundancy check (CRC) characters. The modified RS matrix may store column-centric ECC that may be produced serially. Different types or numbers of ECC may be produced, stored, and provided for different messages stored at different recipients.

A method includes determining a storage modification process for a set of encoded data slices based on a change to the storage parameters associated with storage of data objects in a storage network, where a data segment of the data objects is dispersed storage error encoded into the set of encoded data slices in accordance with dispersed storage error encoding parameters, and where the set of encoded data slices is stored in the storage network. The method also includes executing the storage modification process such that the set of encoded data slices are stored in the storage network in accordance with the changed storage parameters.

The present disclosure provides a decoding method, a decoding device, and a readable storage medium, which include performing an exclusive-or logic operation on a first identification bit and a second identification bit in a first bit stream to obtain a first operation result, and processing the first bit stream according to the first operation result to obtain a second bit stream; performing the exclusive-or logic operation on a third identification bit and a fourth identification bit in the second bit stream to obtain a second operation result, and processing the second bit stream according to the second operation result to obtain a third bit stream; and deleting two specific bits in the third bit stream to obtain a decoded bit.

The present application concerns an iterative bit-flipping decoding method using symbol or bit reliabilities, which is a variation of GRAND decoding and is denoted by ordered reliability bits GRAND (ORBGRAND). It comprises receiving a plurality of demodulated symbols from a noisy transmission channel; and receiving for the plurality of demodulated symbols, information indicating a ranked order of reliability of at least the most unreliable information contained within the plurality of demodulated symbols. A sequence of putative noise patterns from a most likely pattern of noise affecting the plurality of symbols through one or more successively less likely noise patterns is provided. Responsive to the information contained within the plurality of symbols not corresponding with an element of a code-book comprising a set of valid codewords, a first in the sequence of putative noise patterns is used to invert the most unreliable information of the information contained within the plurality of symbols to obtain a potential codeword, and responsive to the potential codeword not corresponding with an element of the code-book, repeatedly: a next likely noise pattern from the sequence of putative noise patterns is applied to invert a noise effect on the received plurality of demodulated symbols to provide a potential codeword, each successive noise pattern indicating an inversion of information for one or more demodulated symbols for a next more reliable combination of information contained within the plurality of symbols, until the potential codeword corresponds with an element of the code-book.

A method for execution by a vault management device of a storage network includes determining a failure impact level to vaults of the storage network based on a failed storage unit within the vaults, where the vaults include a first vault that is associated with a first set of storage units and a first decode threshold number, and a second vault that is associated with a second set of storage units and a second decode threshold number, and where the failure impact level is based on the number of non-failed storage units within each of the vaults. The method continues with determining a failure abatement approach based on the failure impact level. The method continues by with facilitating the failure abatement approach.

Methods and apparatus for transmitting and receiving broadcast signals are provided. The method for transmitting a broadcast signal includes encoding mobile data for forward error correction (FEC), encoding signaling data, forming data groups including the encoded mobile data and the encoded signaling data and transmitting a signal frame that includes the data groups.

Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.

Aspects of the subject disclosure may include, for example, obtaining a received channel-encoded data block having information bits, a transmitted error-check value, and redundant code bits. The redundant code bits correspond to a channel code applied to the received channel-encoded data block prior to transmission via a communication channel. A channel code type is identified and responsive to it being systematic, the information bits and the transmitted error-check value are obtained without decoding according to the channel code. The received channel-encoded data block is checked according to the transmitted error-check value to obtain a result. Responsive to the result not indicating an error, extracting the information bits without decoding the received channel-encoded data block according to the channel code. Responsive to the result indicating an error, decoding the received channel-encoded data block according to the channel code to obtain decoded information bits. Other embodiments are disclosed.

An RFID receiver (1) comprises an antenna (11) configured to receive a radio signal (20) from an RFID transmitter (2) and to generate an electrical signal (110) from the radio signal (20) received from the RFID transmitter (2). A decoder circuit (10) is connected to the antenna (11) and configured to extract from the electrical signal (110) generated by the antenna (11) data bits encoded in the electrical signal (110). The decoder circuit (10) comprises an analog-to-digital converter (12) connected directly to the antenna (11) and configured to generate a digital input signal (13) from the electrical signal (110) generated by the antenna (11). A bit extractor (14) is connected to the analog-to-digital converter (12) and configured to extract the data bits from the digital input (13) signal generated by the analog-to-digital converter (12).