H03M13/47

System and method for combining erasure-coded protection sets

Resource-efficient data protection is performed by generating meta chunks in storage systems that utilize erasure coding. During erasure coding with a k+m configuration, a data chunk can be divided into k data fragments, having indices 1 to k, that can be encoded by combining them with corresponding coefficients of a coding matrix, to generate coding fragments. Source portions that have a reduced set (e.g., less than k data fragments) of data fragments and that are complementary (e.g., that do not have common indices) can be determined and combined to generate a meta chunk. The coding fragments of the source portions can be added to generate coding fragments for the meta chunk, which can then be utilized to recover data fragments of any of the source portions. Further, the coding fragments, that were previously generated by individually encoding each source portion, can be deleted.

System and method for combining erasure-coded protection sets

Resource-efficient data protection is performed by generating meta chunks in storage systems that utilize erasure coding. During erasure coding with a k+m configuration, a data chunk can be divided into k data fragments, having indices 1 to k, that can be encoded by combining them with corresponding coefficients of a coding matrix, to generate coding fragments. Source portions that have a reduced set (e.g., less than k data fragments) of data fragments and that are complementary (e.g., that do not have common indices) can be determined and combined to generate a meta chunk. The coding fragments of the source portions can be added to generate coding fragments for the meta chunk, which can then be utilized to recover data fragments of any of the source portions. Further, the coding fragments, that were previously generated by individually encoding each source portion, can be deleted.

Forward error correction using source blocks with symbols from at least two datastreams with synchronized start symbol identifiers among the datastreams

A forward error correction (FEC) data generator has an input for at least two datastreams for which FEC data shall be generated in a joint manner, each datastream having a plurality of symbols. A FEC data symbol is based on a FEC source block possibly having a subset of symbols of the at least two data streams. The FEC data generator further has a signaling information generator configured to generate signaling information for the FEC data symbol regarding which symbols within the at least two datastreams belong to the corresponding source block by determining pointers to start symbols within a first and a second datastream, respectively, of the at least two datastreams and a number of symbols within the first datastream and second datastreams, respectively, that belong to the corresponding source block.

MANAGING INTEGRITY OF FRAMED PAYLOADS USING REDUNDANT SIGNALS
20200099470 · 2020-03-26 · ·

A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

MANAGING INTEGRITY OF FRAMED PAYLOADS USING REDUNDANT SIGNALS
20200099470 · 2020-03-26 · ·

A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

MEMORY SYSTEM
20200091942 · 2020-03-19 ·

A memory system includes a nonvolatile memory and a memory controller, which determines a read voltage for first data encoded by a first encoding scheme from the nonvolatile memory, by generating a first histogram indicating the number of memory cells for each threshold voltage, and estimating the read voltage using: (a) the first histogram that is corrected based on a first parameter, which is a parameter of the first encoding scheme and a second parameter, which is a parameter of a second encoding scheme, and an estimation function for estimating a read voltage for second data encoded by the second encoding scheme, (b) the uncorrected first histogram, and the estimation function that is corrected based on the first and second parameters, or (c) the first histogram after partial correction based on the first and second parameters, and the estimation function after partial correction based on the first and second parameters.

MEMORY SYSTEM
20200091942 · 2020-03-19 ·

A memory system includes a nonvolatile memory and a memory controller, which determines a read voltage for first data encoded by a first encoding scheme from the nonvolatile memory, by generating a first histogram indicating the number of memory cells for each threshold voltage, and estimating the read voltage using: (a) the first histogram that is corrected based on a first parameter, which is a parameter of the first encoding scheme and a second parameter, which is a parameter of a second encoding scheme, and an estimation function for estimating a read voltage for second data encoded by the second encoding scheme, (b) the uncorrected first histogram, and the estimation function that is corrected based on the first and second parameters, or (c) the first histogram after partial correction based on the first and second parameters, and the estimation function after partial correction based on the first and second parameters.

Wireless communication system, wireless communication device and wireless communication method

A wireless communication system and device improve throughput in a propagation path environment where retransmission is repeated. In a transmission-side wireless communication device, transmission signal storage memories hold bit sequences related to two packet signals for which NACK has been returned, a helper packet generation unit operates the exclusive OR of bit sequences related to two or more of a predetermined number of packet signals held in the transmission signal storage memories, and a coding unit to a transmitting and receiving antenna transmits an auxiliary packet generated by coding a bit sequence of a helper packet that is a result of the exclusive OR operation when the number of packet signals for which NACK has been returned reaches the predetermined number.

Wireless communication system, wireless communication device and wireless communication method

A wireless communication system and device improve throughput in a propagation path environment where retransmission is repeated. In a transmission-side wireless communication device, transmission signal storage memories hold bit sequences related to two packet signals for which NACK has been returned, a helper packet generation unit operates the exclusive OR of bit sequences related to two or more of a predetermined number of packet signals held in the transmission signal storage memories, and a coding unit to a transmitting and receiving antenna transmits an auxiliary packet generated by coding a bit sequence of a helper packet that is a result of the exclusive OR operation when the number of packet signals for which NACK has been returned reaches the predetermined number.

Target FEC (forwarding equivalence class) stack based FEC query in segment routing environments

In one embodiment, a method includes generating a trace request at an initiator node configured for segment routing, the trace request comprising an FEC (Forwarding Equivalence Class) query corresponding to a label in an FEC stack with an unknown FEC, transmitting the trace request on a path with the unknown FEC, and receiving a response to the trace request, the response comprising FEC information including an identifier associated with a label and a forwarding path and representing a class or category of packets. An apparatus is also disclosed herein.