This application relates to determining transmission quality of a communication channel, in particular for determining a measure of errors in data transmitted as multi-bit symbols. Described is an error checker with an input for receiving an input signal comprising a series of modulated symbols, wherein each symbol encodes multiple bits of a pseudo-random bit sequence. A demodulator is configured to receive the input signal and only partially demodulate at least some of the symbols to generate a partially demodulated bit sequence. A PRBS module is configured to receive the partially demodulated bit sequence and determine the pseudo-random bit sequence and a comparator compares the output of the demodulator to an expected output based on the pseudo-random bit sequence determined by the PRBS module.

This application relates to determining transmission quality of a communication channel, in particular for determining a measure of errors in data transmitted as multi-bit symbols. Described is an error checker with an input for receiving an input signal comprising a series of modulated symbols, wherein each symbol encodes multiple bits of a pseudo-random bit sequence. A demodulator is configured to receive the input signal and only partially demodulate at least some of the symbols to generate a partially demodulated bit sequence. A PRBS module is configured to receive the partially demodulated bit sequence and determine the pseudo-random bit sequence and a comparator compares the output of the demodulator to an expected output based on the pseudo-random bit sequence determined by the PRBS module.

An image capturing apparatus including a pixel region in which a plurality of pixels are arranged in a matrix, an A/D converter configured to convert a plurality of signals output from the plurality of pixels into a plurality of corresponding digital data, and a signal processing unit configured to generate an error-correcting code for the plurality of digital data, wherein, in the generating the error-correcting code, the signal processing unit performs grouping the plurality of digital data output from the A/D converter into a plurality of groups, and wherein the signal processing unit performs the grouping so that, in each of the plurality of groups, a total data length of the digital data forming corresponding one of the plurality of groups is not shorter than a length of the error-correcting code.

An image capturing apparatus including a pixel region in which a plurality of pixels are arranged in a matrix, an A/D converter configured to convert a plurality of signals output from the plurality of pixels into a plurality of corresponding digital data, and a signal processing unit configured to generate an error-correcting code for the plurality of digital data, wherein, in the generating the error-correcting code, the signal processing unit performs grouping the plurality of digital data output from the A/D converter into a plurality of groups, and wherein the signal processing unit performs the grouping so that, in each of the plurality of groups, a total data length of the digital data forming corresponding one of the plurality of groups is not shorter than a length of the error-correcting code.

A semiconductor memory device may include a memory core unit including a plurality of memory cells suitable for storing data, an error correction code (ECC) control unit suitable for detecting an error of the data to output a flag signal corresponding to a result of detection of the error, and an address control unit suitable for adjusting a refresh interval of at least one memory cell that stores data in which the error is detected, or repairing the memory cell among the memory cells, in response to the flag signal.

A semiconductor memory device may include a memory core unit including a plurality of memory cells suitable for storing data, an error correction code (ECC) control unit suitable for detecting an error of the data to output a flag signal corresponding to a result of detection of the error, and an address control unit suitable for adjusting a refresh interval of at least one memory cell that stores data in which the error is detected, or repairing the memory cell among the memory cells, in response to the flag signal.

Systems and methods for error correction in structured light are disclosed. In one aspect, a method includes receiving, via a receiver sensor, a structured light image of at least a portion of a composite code mask encoding a plurality of codewords, the image including an invalid codeword. The method further includes detecting the invalid codeword. The method further includes generating a plurality of candidate codewords based on the invalid codeword. The method further includes selecting one of the plurality of candidate codewords to replace the invalid codeword. The method further includes generating a depth map for an image of the scene based on the selected candidate codeword. The method further includes generating a digital representation of a scene based on the depth map. The method further includes outputting the digital representation of the scene to an output device.

A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.