Patent classifications
H04B14/02
MULTI-LEVEL OUTPUT DRIVER WITH ADJUSTABLE PRE-DISTORTION CAPABILITY
A PAM (Pulse Amplitude Modulation) modulator driver is configured to receive a PAM input signal having N input amplitude levels and provide a PAM output signal having N output amplitude levels, where N is an integer. The PAM modulator driver circuit configured to electrically adjust amplitude levels in the PAM output signal.
PAM-4 calibration
A hybrid voltage mode (VM) and current mode (CM) four-level pulse amplitude modulation (PAM-4) transmitter circuits (a.k.a. drivers) is calibrated using a configurable replica circuit and calibration control circuitry. The replica circuit includes an on-chip termination impedance to mimic a receiver's termination impedance. The amount of level enhancement provided by the current mode circuitry is calibrated by adjusting the current provided to the output node and sunk from the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving an intermediate PAM-4 level. After the level enhancement has been set, the non-linearity between levels is calibrated by adjusting the amount of current provided to the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving a maximum output voltage level.
Probabilistic signal shaping using multiple codebooks
A communication system in which multiple shaping codes are selectively and iteratively used to encode a data frame such that possible energy inefficiencies associated with the use of constant-probability codes and/or transmission of dummy constellation symbols can be relatively small. In an example embodiment, the used shaping codes have different respective code rates, and a code selector of the shaping encoder operates to select one of the shaping codes by adaptively matching the rate of the code to the effective rate needed to efficiently encode the unprocessed portion of the data frame. The encoding is carried out in a manner that enables the shaping decoder to unequivocally determine the shaping codes that have been used for encoding each particular data frame based on the same rate-matching criteria as those used by the shaping encoder. At least some embodiments advantageously lend themselves to being implemented using circuits of relatively low complexity.
Methods and Apparatuses for Signaling with Geometric Constellations
Communication systems are described that use signal constellations, which have unequally spaced (i.e. ‘geometrically’ shaped) points. In many embodiments, the communication systems use specific geometric constellations that are capacity optimized at a specific SNR. In addition, ranges within which the constellation points of a capacity optimized constellation can be perturbed and are still likely to achieve a given percentage of the optimal capacity increase compared to a constellation that maximizes d.sub.min, are also described. Capacity measures that are used in the selection of the location of constellation points include, but are not limited to, parallel decode (PD) capacity and joint capacity.
Monolithically integrated system on chip for silicon photonics
The present invention includes an integrated system-on-chip device configured on a substrate member. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The input/output block comprises a SerDes block, a CDR block, a compensation block, and an equalizer block. The SerDes block is configured to convert a first data stream of N having a first predefined data rate at a first clock rate into a second data stream of M having a second predefined data rate at a second clock rate. The device has a driver module provided on the substrate member and coupled to a signal processing block, and a driver interface provided on the substrate member and coupled to the driver module and a silicon photonics device.
NETWORK TRANSCEIVER WITH VGA CHANNEL SPECIFIC EQUALIZATION
A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.
Apparatus for a single edge nibble transmission (SENT) multi transmission mode
Methods, systems, and apparatuses for a single edge nibble transmission (SENT) multi-transmission mode are described. In an example, a system can include a transmitter and a receiver connected to one another. The transmitter may encode an identifier of a device in a synchronization nibble of a SENT signal. The transmitter may transmit the SENT signal with the encoded identifier to the receiver. The receiver may receive the SENT signal from the transmitter. The receiver may decode the identifier of the device from the synchronization nibble of the SENT signal to identify the device.
Multi-level output driver with adjustable pre-distortion capability
A PAM (Pulse Amplitude Modulation) modulator driver is configured to receive a PAM input signal having N input amplitude levels and provide a PAM output signal having N output amplitude levels, where N is an integer. The PAM modulator driver circuit configured to electrically adjust amplitude levels in the PAM output signal.
Network transceiver with VGA channel specific equalization
A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.
Soft FEC with parity check
A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.