H04B15/005

Apparatus and method for measuring power supply noise
10079648 · 2018-09-18 · ·

Described is an apparatus which comprises: a power delivery distribution network (PDN) to provide a power supply to at least one circuit; and an on-die synchronous power supply noise injector to inject noise to the power supply on the PDN. Described is another apparatus which comprises: a PDN to provide power supply to various circuits; an on-die power supply noise (PSN) sampler to sample the power supply with an injected noise, wherein the PSN sampler to sample the power supply with at least two different clock signals; and a phase noise accumulator to randomize the periods of the at least two different clock signals.

Aggregate signal amplification device and method
10069527 · 2018-09-04 · ·

A surface acoustic wave (SAW) filter that receives an aggregate circuit and outputs two or more sub-signals on outputs each of a different frequency band. The sub-signals are amplified by low noise amplifiers and, in one implementation, the amplified sub-signals can be summed. The outputs are connected via a switched passive network so that portions of the sub-signals on the outputs that are not in the selected frequency band are at least partially terminated.

Transceiver for communication and method for controlling communication

An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

CIRCUIT, METHOD, AND RECEIVER APPARATUS FOR PERFORMING ON-THE-FLY IQ MISMATCH COMPENSATION
20180241606 · 2018-08-23 ·

A method employed by a circuit included within a receiver apparatus and configured for performing IQ mismatch compensation when receiver apparatus is operating under data reception mode includes: transforming a data signal, which is generated by a radio frequency receiver under the data reception mode, from time domain into a plurality of frequency bin signals in frequency domain; calculating to obtain at least one frequency domain calibration parameter according to the plurality of frequency bin signals in frequency domain; and, updating at least one coefficient parameter of IQ mismatch compensation according to the obtained at least one frequency domain calibration parameter, to make IQ mismatch compensation compensate IQ mismatch based on the updated at least one coefficient parameter.

Communication system
10050724 · 2018-08-14 · ·

The present disclosure provides a communication system. The communication system includes a radio wave receiver; a transmission node that transmits data; and a reception node that receives the data from the transmission node. The transmission node changes a transmission rate of the data so that a notch point at which a spectrum of a communication waveform decreases overlaps with a frequency selected by the radio wave receiver.

RF switch with integrated tuning
10038409 · 2018-07-31 · ·

Methods and devices are described for reducing receiver complexity in an RF front-end stage. In one exemplary implementation, a switch is used to connect a plurality of receive paths to a single input amplifier of a transceiver unit used the RF front-end stage. In another exemplary implementation, the switch has a tunable network which can be tuned with respect to various frequencies of operation of the receive path and associated RF signal.

SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR SYSTEM, AND ELECTRIC SOURCE VOLTAGE CONTROL METHOD
20180212691 · 2018-07-26 · ·

A semiconductor integrated circuit includes a voltage comparison circuit and a control circuit. The voltage comparison circuit compares a detection voltage with a reference voltage. The detection voltage is a detected result of an electric source voltage supplied from an electric source supply device supplying the electric source voltage. The reference voltage is set to be lower than a standard voltage used in stabilization control that the electric source supply device performs for stabilizing the electric source voltage. The control circuit performs control of compensating a voltage drop of the electric source voltage when the detection voltage is lower than the reference voltage based on a result of comparison by the voltage comparison circuit.

Noise detection device, noise detection method, and noise detection program
10020005 · 2018-07-10 · ·

A frame signal generator is configured to generate a frame signal with a predetermined first time length from an input signal. A reference signal generator is configured to generate a reference signal from a signal located more in a past than a position of the frame signal in the input signal. A correlation value calculator is configured to calculate a correlation value between the frame signal and the reference signal within a range of a predetermined phase shift amount m. A periodic noise determiner is configured to determine whether or not the frame signal includes periodic noise, and calculate a period of the periodic noise in the case where the frame signal includes the periodic noise. A correlation value calculation range generator is configured to generate the range of the predetermined phase shift amount based on the period of the periodic noise.

LOW POWER SYSTEM AND METHOD FOR DSL LINES
20180176387 · 2018-06-21 ·

The transmit power level of a transceiver coupled to a digital subscriber line (DSL) line is reduced from a first transmit power level sufficient for the transceiver to continuously transmit data on the DSL line at a first bit rate to a second transmit power level below the first transmit power level sufficient for the transceiver to continuously transmit data on the DSL line at a second bit rate that is lower than the first bit rate. The reduction in transmit power is limited so that the change does not induce time-varying crosstalk sufficient to destabilize a nearby DSL line. While the transmit power level of the transceiver is reduced to the second transmit power level, the transceiver is suspended from transmitting data on the DSL line for repeated periods of time. Suspending the data transmission is controlled to avoid further time-varying crosstalk sufficient to destabilize the nearby DSL line.

Wake-up circuit in receiving device and method of operating the receiving device

A receiving device and a method for operating a receiving device are provided in which a signal is divided into two separate signal parts. The two signal parts are demodulated simultaneously and, from the demodulated signals, the difference is formed. After the formation of the difference, an information item is obtained from the difference signal and compared with a predetermined information item. In the case of correspondence of the obtained information and the compared information, a wake-up signal is generated.