A physical layer circuit of a receiver, a clock recovery circuit and a calibration method of frequency offset are provided. The physical layer circuit includes an equalizer and a clock recovery circuit. The equalizer generates an equalized sampling signal corresponding to a sampling clock signal. The clock recovery circuit includes a phase detector, a loop filter, a free wheel circuit, an output circuit and a controller. The phase detector calculates phase differences according to the equalized sampling signal. The loop filter generates loop pulses according to the phase differences. The free wheel circuit generates free wheel pulses. The output circuit receives the loop pulses and the free wheel pulses and generates corresponding phase-shifting pulses for adjusting the sampling clock signal. The controller calculates an accumulative correction offset according to the phase-shifting pulses, and the free wheel circuit periodically generates the free wheel pulses accordingly.

A CDR circuit includes: a comparison circuit that receives data signal on which a first clock signal is superimposed, and outputs a comparison result obtained by comparing the data signal with three different threshold values at a timing synchronized with a second clock signal; a data pattern detection circuit that detects an occurrence of a data pattern, based on the comparison result; a frequency detection circuit that outputs, when an occurrence of the data pattern is detected, a detection result indicating whether a second frequency of the second clock signal is higher than a first frequency of the first clock signal; an adjustment circuit that outputs, based on the detection result, an adjustment signal for adjusting a phase of the second clock signal and the second frequency; and an oscillator circuit that outputs the second clock signal with the phase and the second frequency adjusted, based on the adjustment signal.

A physical layer circuit of a receiver, a clock recovery circuit and a calibration method of frequency offset are provided. The physical layer circuit includes an equalizer and a clock recovery circuit. The equalizer generates an equalized sampling signal corresponding to a sampling clock signal. The clock recovery circuit includes a phase detector, a loop filter, a free wheel circuit, an output circuit and a controller. The phase detector calculates phase differences according to the equalized sampling signal. The loop filter generates loop pulses according to the phase differences. The free wheel circuit generates free wheel pulses. The output circuit receives the loop pulses and the free wheel pulses and generates corresponding phase-shifting pulses for adjusting the sampling clock signal. The controller calculates an accumulative correction offset according to the phase-shifting pulses, and the free wheel circuit periodically generates the free wheel pulses accordingly.

In embodiments of the present invention improved capabilities are described for systems and methods that provide for a power outage lighting management within an environment, comprising a power outage detection device adapted to detect a power outage condition and to wirelessly transmit power outage indication data to a plurality of lighting systems within the environment, where at least one of the plurality of lighting systems include an LED light source that is powered by an internal power source.

Embodiments are generally directed to signal phase optimization in memory interface training. An embodiment of an apparatus includes an interface for at least one signal; and interface training logic capable of automatically adjusting a phase relationship between the signal and a strobe or clock, including establishing a phase delay of the signal and a phase delay of the strobe or clock for training of the interface, wherein the interface training logic is capable of determining a phase delay reduction for the signal subsequent to measurement of an eye margin for the signal, the phase delay reduction to retain a sufficient delay to maintain the eye margin for sampling of the signal.

An apparatus is provided which comprises: a data slicer to receive first data sampled by a data clock; an edge slicer to receive second data sampled by an edge clock; and a Least Mean Square (LMS) circuitry coupled to the data and edge slicers, wherein the LSM circuitry is to generate a code to adjust a phase of one of data clock and/or edge clock relative to one another.

System and method of frame alignment at a receiver with power optimization mechanisms. A framer uses one or more comparators to search for the FAW in the incoming data, with each comparator configured to serially compare multiple windows of a parallel M-bit block (as provided from a parallel data bus) with the FAW. Multiple comparators in the framer may operate in parallel to search for the FAW at different windows. This configuration can significantly reduce the comparator count and so the gate count as well as the chip area in a framer. Power consumption can be advantageously reduced as one comparator operating serially consumes less power than multiple comparators in parallel because less gate toggling is involved.

A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.