A clock recovery device is provided. The clock recovery device includes a clock data recovery circuit and a fast relock circuit. The clock data recovery circuit is configured to generate an output clock signal in response to an input clock signal. The clock data recovery circuit includes a charge pump for generating a control voltage and a voltage controlled block for generating the output clock signal based on the control voltage. The fast relock circuit is configured to convert a comparison signal indicating a comparison result between the input clock signal and the output clock signal to an analog output voltage. When the charge pump is disabled, an output path of the fast relock circuit is turned on, and the analog output voltage is applied to an input of the voltage controlled block.

A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.

Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.

A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.

A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

A communications device transmitting data to and receiving data from a mobile communications network, includes a transmitter, a receiver, and a controller configured to control the transmitter and receiver to transmit and receive the data via a wireless access interface. The controller is configured to identify during an initialization phase, from received information, a predetermined priority for synchronizing the transmitter and receiver, the predetermined priority including at least one of a global navigation signal, a regional navigation signal and a synchronization signal received from another communications device, the global navigation signal and the regional navigation signal having a higher priority than the synchronization signal received from the other communications device, and to control the transmitter and the receiver to synchronize the transmitting and the receiving based on a selected one of the global navigation signal, the regional navigation signal, and the synchronization signal in accordance with the predetermined priority.

A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

A clock data recovery (CDR) circuit includes: a band select circuit, a low dropout regulator (LDO), a charge pump and a voltage-controlled oscillator (VCO), wherein the band select circuit is arranged to generate a digital signal according to at least a reference voltage; the LDO is arranged to regulate a ground voltage, wherein the LDO adjusts an operating band of the LDO by receiving at least a part of the digital signal to adjust a bias current of an amplifier of the LDO; the charge pump is arranged to generate a control voltage according to at least a part of the digital signal; and the VCO is arranged to generate a clock signal according to the control voltage, wherein the VCO adjusts an operating band of the CDR circuit by receiving at least a part of the digital signal to adjust a bias current of the VCO.

Prior to joining a device to a network, the device is connected to an external system via a local connection. The external system provides the device with a local time stamp that includes a local time value and a local time error value. The device may use the time information to communicate with the external system. After the device is joined to the network, the device may transmit a communication on the network that includes time information. If so, then the communication includes a time value based on the device's time value and a time error value set to a value indicating a maximum error. The network is protected from potentially poor quality time information. Any device that receives the communication rejects the time information since the time error value indicates a maximum error.

System and method of frame alignment at a receiver with power optimization mechanisms. A framer is configured to perform a frame alignment process on a data stream and enter an inactive state after frame alignment is achieved. In the inactive state, the circuits used to perform the frame alignment process in the framer can be powered down or otherwise placed in a power reduction mode. Responsive to an indication that data processing at the receiver becomes out-of-frame again, the framer can wake up from the inactive state and restart the frame alignment process. An out-of-frame indication may be generated by error detection logic (e.g., forward error correction (FEC) decoder) when it detects an excessive number of uncorrectable errors.