A clock data recovery circuit includes a phase locked loop (PLL), a code signal generator, and a clock and data generator. The PLL generates a plurality of reference clock signals of which frequencies are modulated. Each of the plurality of reference clock signals has a first profile that is periodically fluctuated. The code signal generator generates a first compensation code signal. The first compensation code signal has a second profile that is periodically fluctuated and is different from the first profile. The clock and data generator generates a recovered data signal by sampling an input data signal based on a clock signal, compensates a frequency modulation on the plurality of reference clock signals based on the first compensation code signal, and includes a phase interpolator that generates the clock signal based on the plurality of reference clock signals and the first compensation code signal.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Introduced here are techniques for implementing a clock and data recovery circuit with improved tendencies, such a pull up and/or pull down tendencies. In various embodiments, the CDR circuit includes a phase detector that receives an input signal and a output reference clock signal. The phase detector then outputs two signals to charge pump. The output from the charge pump drives an oscillator control voltage up or down depending the current from the charge pump. A lock detector detects whether a lock has occurred by comparing the oscillator control voltage to a predetermined threshold voltage. A lock can occur when the circuit has settled into a frequency substantially near the frequency of the input signal and the oscillator control voltage is substantially near the threshold voltage. A controller circuit can control a sweeping of an available frequency range by the circuit until a lock occurs.

In an example, a synchronization signal can be transmitted to a plurality of synchronizers. The plurality of synchronizers can include a plurality of upstream synchronizers and a downstream synchronizer. Each synchronizer of the plurality of upstream synchronizers can be caused to count from a respective count value until a predetermined end count sequence value in response to receiving the synchronization signal. The respective count value stored at each synchronizer can be representative of a difference in time between a respective upstream synchronizer of the plurality of upstream synchronizers receiving the synchronization signal and the downstream synchronizer receiving the synchronization signal. A respective processing element of a plurality of processing elements can be caused to start a respective function or operation in response to a respective upstream synchronizer reaching the predetermined end count sequence value.

A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

A clock data recovery unit includes: a phase corrector generating a first compensation clock signal and a second compensation clock signal based on an external clock signal; and a transition detector, wherein the transition detector comprises: a first integrator configured to integrate a first training pattern signal according to the first compensation clock signal to provide a first integration signal; and a second integrator configured to integrate the first training pattern signal according to the second compensation clock signal to provide a second integration signal, wherein, in response to the first integration signal being greater than a first reference voltage and the second integration signal being less than the first reference voltage, occurrence of a transition of the first training pattern signal is detected.

A time information obtaining method is provided, including: receiving a first message (201), where the first message includes at least one piece of time information, and each piece of time information corresponds to a respective clock source; and obtaining, from the first message, time information corresponding to a clock source required by a terminal (202). A time information transmission method, a terminal, and a network device are further provided.

According to one embodiment, there is provided a semiconductor integrated circuit including a first equalizer and a clock reproduction circuit. The first equalizer boosts a data signal. The clock reproduction circuit extracts from the boosted data signal information of a pair consisting of a rise edge and a fall edge which are temporarily separated from each other by N or more times (N is an integer of two or higher) as much as a clock cycle, performs a phase adjustment based on the information about the pair of the rise edge and the fall edge, and reproduces a clock.

A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.