A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

Receivers, controller units for receivers and related methods are provided. One receiver includes an adjustable sample provider providing samples of an input signal using an adjustable sample timing and a feedback path providing a feedback signal to the adjustable sample provider based on a timing error. The feedback path includes a loop filter providing sample timing information to the adjustable sample provider and a replacement value provider providing a replacement sample timing information replacing the sample timing information when an input signal does not fulfil a predetermined requirement for a feedback-based sample timing adaptation. The replacement value provider provides the replacement sample timing information considering a timing error information over a longer time period when compared to a time period considered by the loop filter for a provision of the sample timing information.

There are provided examples of receivers, controller units and related methods, wherein one receiver includes: an adjustable sample provider configured to provide samples of an input signal using an adjustable sample timing; a feedback path configured to provide a feedback signal to the adjustable sample provider on the basis of a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the adjustable sample provider; and a replacement value provider configured to provide a replacement sample timing information replacing the sample timing information provided by the feedback path when an input signal does not fulfil a predetermined requirement for a feedback-based sample timing adaptation, wherein the replacement value provider is configured to provide the replacement sample timing information considering a timing error information, or a quantity derived from the timing error information, over a longer time period when compared to a time period considered by the loop filter for a provision of the sample timing information.

Embodiments of this application disclose a phase detection method, a phase detection circuit, and a clock recovery apparatus. The method includes: receiving a first signal, and deciding a (2M1) level of the first signal to obtain a decision result, where the first signal is a (2M1)-level signal, and M is a positive integer: obtaining a response amplitude parameter of a transmission channel; extracting clock phase information in the first signal based on the first signal, the decision result, and the response amplitude parameter; and determining output clock phase information based on at least three decision results and at least three pieces of clock phase information in at least three symbol periods. According to the foregoing method, a stable phase detection gain can be achieved when a clock phase is tuned to a pulse response edge

A media system, method, and a computer program product for synchronizing device clocks including a plurality of devices having device clocks, where each device is capable of independently selecting a primary clock device from the plurality of devices to coordinate clock synchronization of the remaining devices, e.g., secondary devices. Each device can utilize the same criteria or set of rules to select the primary clock device from among the plurality of devices after an initial exchange of data during a discovery phase. The selection of the primary clock device can be based on random or arbitrary selection, or based on at least one devices characteristic exchanged within the data obtained during the discovery phase. Once selected, the primary clock device coordinates a clock synchronization sequence with each secondary device until each secondary device clock is synchronized to within a predetermined threshold with the primary clock of the primary clock device.

A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.

A CDR method/circuit utilizes a closed-loop clock alignment circuit and a duplicate clock to align a sampling point clock to both mid-interval and optimal sample point phases during data receiving processes. An initial clock is generated having the mid-interval sampling point phase, then the closed-loop clock alignment circuit generates a phase correction signal based on a phase difference between the data sampling clock and the initial clock, and then the phase correction signal is fed back to a high-speed phase mixer to adjust/align the sampling point clock to the initial clock. Subsequently, the duplicate clock is generated and utilized to determine an optimal sampling point phase while the data sampling clock is utilized to read the received data signal, and then the closed-loop clock alignment circuit is re-used to re-align the data sampling clock to the duplicate clock when the optimal sampling point phase is identified.

According to one embodiment, there is provided a semiconductor integrated circuit including a first equalizer and a clock reproduction circuit. The first equalizer boosts a data signal. The clock reproduction circuit extracts from the boosted data signal information of a pair consisting of a rise edge and a fall edge which are temporarily separated from each other by N or more times (N is an integer of two or higher) as much as a clock cycle, performs a phase adjustment based on the information about the pair of the rise edge and the fall edge, and reproduces a clock.

A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data, packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.