Provided are a phase detection method and apparatus for a clock signal, and a communication device. A clock signal of a clock to be detected is sampled according to sampling periods set by a sampling clock; a phase angle value corresponding to a sampled clock signal in a current sampling period is obtained according to a mapping relationship between sampled signals and phase angle values; a phase difference corresponding to the current sampling period is subtracted from the phase angle value to obtain an initial phase value of the clock to be detected in the current sampling period, wherein the phase difference is a phase difference between the clock to be detected and the sampling clock in the current sampling period; and after the sampling ends, a final phase value of the clock to be detected is obtained according to initial phase values obtained in respective sampling periods.

Adaptive payload extraction in wireless communications involving multi-access address packets are described herein. A device can be configured to detect a synchronization sequence of a nested data packet, the nested data packet having synchronization sequences placed in series ahead of a payload, the synchronization sequences including the synchronization sequence; evaluate blocks after the synchronization sequence in the nested data packet to identify the blocks as either additional ones of the synchronization sequences or the payload in the nested data packet; and extract the payload.

A phase calibration method includes sweeping phase codes applicable to a serial clock signal, identifying a first, a second, a third, and a fourth phase code, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value, determining an average phase code based on the identified phase codes.

Tenants in data centers may want access to high precision clocks without having to run their own PTP stacks or reference clocks. Furthermore, different tenants may want their workloads synchronized to their own secured clock domain. PTP, the currently dominant synchronization protocol, allows for only 256 clock domains (CDs). Virtual CDs (vCDs) virtualize the concept of clock domains by maintaining a hardware clock within a host computer, receiving a network clock domain packet that includes a clock domain identifier and an origin timestamp produced by a reference clock, using the network clock domain packet to synchronize the hardware clock to the reference clock, and using the hardware clock to provide a hardware timestamp value to a virtual machine (VM) running on the host computer or to a process running on the host computer, wherein the hardware clock is secured from manipulation by the VM or by the process.

Examples described herein include systems and methods for performing email synchronization in situations where mobile-device connectivity is lacking. The mobile device can send an SMS message to an email notification server requesting email synchronization and the email notification server can request synchronization with the email server associated with the user's email account. After receiving an email from the email server, the email notification server can encrypt the email and break it into various chunks, with each chunk including a header having identifying information. The chunks can be transmitted as SMS messages to the mobile device. The email application can retrieve the SMS messages, decrypt them, and reconstruct the email. The email application can then display the email for the user.

Provided are a clock synchronization method performed between communication nodes included in a communication network, the clock synchronization method comprises receiving a synchronization source signal through any one of remaining communication nodes except for an uppermost communication node included in the communication network, generating a reference clock for clock synchronization from the received synchronization source signal and transmitting the generated reference clock through a first path including at least a portion reverse to a second path through which a downlink signal is transmitted in the communication network.

A transceiver device includes a transmitter and a receiver connected through first and second lines. A first frame period includes an active period for transmitting a first payload and a vertical blank period including a frequency hopping period. The transmitter transmits, to the first and second lines, signals having a first voltage range in a first mode and signals having a second voltage range in a second mode. The transmitter generates a first horizontal synchronization signal in the second mode except for the frequency hopping period, encodes the first horizontal synchronization signal to horizontal synchronization data, and generates a second horizontal synchronization signal in the first mode in the frequency hopping period. The transmitter adds a first clock training pattern to the horizontal synchronization data except for the frequency hopping period, and adds a second clock training pattern to first horizontal synchronization data after the frequency hopping period.

In an example, a synchronization signal can be transmitted to a plurality of synchronizers. The plurality of synchronizers can include a plurality of upstream synchronizers and a downstream synchronizer. Each synchronizer of the plurality of upstream synchronizers can be caused to count from a respective count value until a predetermined end count sequence value in response to receiving the synchronization signal. The respective count value stored at each synchronizer can be representative of a difference in time between a respective upstream synchronizer of the plurality of upstream synchronizers receiving the synchronization signal and the downstream synchronizer receiving the synchronization signal. A respective processing element of a plurality of processing elements can be caused to start a respective function or operation in response to a respective upstream synchronizer reaching the predetermined end count sequence value.

A system is provided that includes a first electronic device, multiple second electronic devices coupled to the first electronic device via respective interfaces, and a clock generator coupled to the second electronic devices and configured to generate and provide a clock signal to each of the second electronic devices for clocking operation of the second electronic devices. The clock signal is a gapped clock signal having at least one gap created by the clock generator removing one or more clock pulses based on a synchronization signal, and the second electronic devices are configured to synchronize data transmission between the second electronic devices and the first electronic device via the interfaces using the at least one gap in the gapped clock signal to align the data transmission.

A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range smaller than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload in the second mode to generate a first payload, and transmits the clock training pattern and the first payload through the first line and the second line.