An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.

A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the ¼-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLF.sub.INV(s). The VLF.sub.INV(S) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a −3-dB corner frequency of 40 MHz.

A full-duplex communication device includes an antenna, a transceiving module a conversation module and a control module. The antenna is configured to receive and send signals. Two of the transceiving module are provided, the transceiving module is installed with a filter and a gating switch connecting to the filter, operating frequencies of the two transceiving module are different, and the gating switche is configured to switch operating states between a receiving mode and a sending mode of the transceiving modules. The conversation module is connected to the transceiving modules and configured to receive and play voice signals. The control module is connected to the transceiving modules and configured to control tasks of the transceiving modules.

A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.

A method for a slave device for calibrating an output timing for transmitting data to a master device is provided. The master and slave devices are communicatively coupled via an interface. The method includes: receiving, from the master device, one or more consecutive first signal edges indicating a synchronization event; recovering a reference clock of the master device based on the one or more consecutive first signal edges; transmitting one or more predetermined second signal edges to the master device and generated using the recovered reference clock; receiving, from the master device, data indicating one or more sampled values of the master device for the one or more predetermined second signal edges; and adjusting the output timing based on a comparison of the one or more predetermined second signal edges and the one or more sampled values of the master device for the one or more predetermined second signal edges.

A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.

A monitoring device includes: an acquisition unit for acquiring a clock signal output from a communication circuit that outputs the clock signal; and a monitoring unit for analyzing the waveform of the clock signal acquired by the acquisition unit, based on a predetermined reference clock signal having a period equal to or shorter than a period of the clock signal to thereby determine whether or not there is a sign of malfunction in the communication circuit.

Techniques for computer security, and more specifically timestamp-based key generation techniques, are described. Some implementations provide a table of key generation processes that is shared as a secret between a first computing system and a second computing system, both of which have synchronized clocks. Both computing systems use the same technique for selecting a key generation process from the table, such as based on a random number generator seeded with a timestamp. Since the computing systems have synchronized clocks, they both select and use the same key generation process, thereby generating the same encryption key without the need to communicate the key from one system to another. Furthermore, both computing systems may synchronize their clocks to a private time server that maintains a clock that runs faster or slower than standard time. Security is maintained by one or more of restricting access to the time server, using secret key generation processes, and/or using a secret random number generator.

A device includes a transmitter to transmit serialized data within a differential direct-current (DC) signal over a differential output line, a multiplexer circuit coupled to the transmitter, and a calibration circuit coupled between the differential output line, a multi-phase clock, and the multiplexer circuit. The multiplexer circuit is to select the serialized data from ones of multiple input lines according to a multi-phase clock and pass the selected serialized data to the transmitter. The serialized data includes a calibration bit pattern. The calibration circuit is to capture and digitize the differential DC signal into a digital stream, measure an error value from the digital stream that is associated with distortion based on the calibration bit pattern, convert the error value into a gradient value, and correct one or more phases of the multi-phase clock to compensate for the distortion based on the gradient value.

A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.